On Fri, Aug 04, 2017 at 08:20:32PM +1000, Daniel Axtens wrote:
> A system without PCI legacy resources (e.g. ARM64, powerpc) may
> find that no default/boot VGA device has been marked, because the
> VGA arbiter checks for legacy resource decoding before marking a
> card as default.
Would it be fea
On Fri, 04 Aug 2017 21:54:57 +0200
Andreas Schwab wrote:
> No, this is really a 4.13-rc1 regression.
>
> Andreas.
>
SLB miss with MSR[RI]=0 on
lbz r0,THREAD+THREAD_LOAD_FP(r7)
Caused by bc4f65e4cf9d6cc43e0e9ba0b8648cf9201cd55f
Hmm, I'll see if something can be done, but that MSR_RI stuf
The first 9 patches are a bunch of independent small cleanups
and improvements I've collected. The next 4 are improvements to
POWER9 idle state entry and exit. They significantly change how
we enter idle, now in virtual mode and without ptesync. EC=0 idle
is significantly simplified from there, and
Interrupts which do not require EE to be cleared can all
be tested with a single bitwise test.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/kernel/exceptions-64s.S | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/kernel/exceptions-64s.S
b/arch/powerpc/ke
EE is always enabled in SRR1 for masked interrupts, so clearing
it can use xor.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/kernel/exceptions-64s.S | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/powerpc/kernel/exceptions-64s.S
b/arch/powerpc/kernel/exceptions-64s
Places in the kernel where r13 is not the PACA pointer must have
maskable interrupts disabled, so r13 does not have to be restored
when returning from a soft-masked interrupt.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/kernel/exceptions-64s.S | 2 +-
1 file changed, 1 insertion(+), 1 deleti
Move the clearing of irq_happened bits into the condition where
they were found to be set. This reduces instruction count slightly,
and reduces stores into irq_happened.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/kernel/irq.c | 45 +++--
1 file change
This results in smaller code, and fewer branches.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/kernel/entry_64.S | 6 +-
arch/powerpc/kernel/exceptions-64s.S | 2 +-
arch/powerpc/kernel/irq.c| 2 --
3 files changed, 2 insertions(+), 8 deletions(-)
diff --git a/arch/powe
POWER9 host external interrupts use the h_virt_irq_common handler, so
use that to replay them rather than using the hardware_interrupt_common
handler. Both call do_IRQ, but using the correct handler reduces i-cache
footprint.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/kernel/exceptions-64s.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/kernel/entry_64.S | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S
index ec67f67dafab..3f2666d24a7e 100644
--- a/arch/powerpc/kernel/entry_64.S
+++ b/arch/powerpc/kernel/entry_64.S
@@
HVI interrupts have always used 0x500, so remove the dead branch.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/kernel/exceptions-64s.S | 2 --
1 file changed, 2 deletions(-)
diff --git a/arch/powerpc/kernel/exceptions-64s.S
b/arch/powerpc/kernel/exceptions-64s.S
index 29253cecf713..566cf126
The CTRL register is read-only except bit 63 which is the run latch
control. This means it can be updated with a mtspr rather than
mfspr/mtspr.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/kernel/process.c | 35 +++
1 file changed, 27 insertions(+), 8 deletions
POWER9 CPUs have independent MMU contexts per thread so KVM
does not have to bring sibling threads into real-mode when
switching MMU mode to guest. This can simplify POWER9 sleep/wake
paths and avoids hwsyncs.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/include/asm/kvm_book3s_asm.h | 4
Signed-off-by: Nicholas Piggin
---
arch/powerpc/kernel/idle_book3s.S | 7 ---
arch/powerpc/kvm/book3s_hv_rmhandlers.S | 24
2 files changed, 16 insertions(+), 15 deletions(-)
diff --git a/arch/powerpc/kernel/idle_book3s.S
b/arch/powerpc/kernel/idle_book3s.S
i
The hardware can execute stop in any context, and KVM does not
require real mode. This saves a switch to real-mode when going
idle.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/kernel/idle_book3s.S | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/powerpc/kernel/idle_book3s.S
When stop is executed with EC=ESL=0, it appears to execute like a
normal instruction (resuming from NIP when woken by interrupt).
So all the save/restore handling can be avoided completely. In
particular NV GPRs do not have to be saved, and MSR does not have
to be switched back to kernel MSR.
So m
On Sun, 6 Aug 2017 03:02:41 +1000
Nicholas Piggin wrote:
> When stop is executed with EC=ESL=0, it appears to execute like a
> normal instruction (resuming from NIP when woken by interrupt).
> So all the save/restore handling can be avoided completely. In
> particular NV GPRs do not have to be s
binutils >= 2.26 now warns about misuse of register expressions in
assembler operands that are actually literals, for example:
arch/powerpc/kernel/entry_64.S:535: Warning: invalid register expression
Signed-off-by: Andreas Schwab
---
arch/powerpc/include/asm/ppc_asm.h | 2 +-
arch/powerpc/kern
On Sun, 2017-08-06 at 03:02 +1000, Nicholas Piggin wrote:
> The hardware can execute stop in any context, and KVM does not
> require real mode. This saves a switch to real-mode when going
> idle.
+Paulus.
> Signed-off-by: Nicholas Piggin
> ---
> arch/powerpc/kernel/idle_book3s.S | 9 +
>
On Sun, 2017-08-06 at 03:02 +1000, Nicholas Piggin wrote:
> HVI interrupts have always used 0x500, so remove the dead branch.
Maybe we should fix that and "catch" in incorrect entry via 0x500
which would mean the XIVE is trying to deliver guest irqs to the OS...
That can happen if some LPCR bits
On Sun, 06 Aug 2017 09:00:32 +1000
Benjamin Herrenschmidt wrote:
> On Sun, 2017-08-06 at 03:02 +1000, Nicholas Piggin wrote:
> > HVI interrupts have always used 0x500, so remove the dead branch.
>
> Maybe we should fix that and "catch" in incorrect entry via 0x500
> which would mean the XIVE i
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