-software-pagetables/20170723-002848
base: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git next
config: powerpc-akebono_defconfig (attached as .config)
compiler: powerpc-linux-gnu-gcc (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
wget
https://raw.githubusercontent.com/01org
Hi Santosh,
[auto build test ERROR on powerpc/next]
[also build test ERROR on v4.13-rc1 next-20170721]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Santosh-Sivaraj/powerpc-vdso64-Add-support-f
Hi Ard,
> But the fact remains that we are going about this the wrong way.
> Whether a graphics card decodes legacy VGA ranges or not has *nothing*
> to do with whether or not it is in fact the primary device on a
> non-x86 system, and so I still think the VGA arbiter should be omitted
> entirely
On Fri, Jul 21, 2017 at 04:51:39PM +0200, Laurent Vivier wrote:
> As for commit 68baf692c435 ("powerpc/pseries: Fix of_node_put()
> underflow during DLPAR remove"), the call to of_node_put()
> must be removed from pSeries_reconfig_remove_node().
>
> dlpar_detach_node() and pSeries_reconfig_remove_
This patch adds emulation of the cmpb instruction, enabling xmon to
emulate this instruction.
Tested for correctness against the cmpb asm instruction on ppc64le.
Signed-off-by: Matt Brown
---
v2:
- fixed opcode
- fixed mask typecasting
---
arch/powerpc/lib/sstep.c | 20 +
This adds emulations for the popcntb, popcntw, and popcntd instructions.
Tested for correctness against the popcnt{b,w,d} instructions on ppc64le.
Signed-off-by: Matt Brown
---
v2:
- fixed opcodes
- fixed typecasting
- fixed bitshifting error for both 32 and 64bit arch
---
This adds emulation for the bpermd instruction.
Tested for correctness against the bpermd instruction on ppc64le.
Signed-off-by: Matt Brown
---
v2:
- fixed opcode
- added ifdef tags to do_bpermd func
- fixed bitshifting errors
---
arch/powerpc/lib/sstep.c | 24 +++
This add emulation for the prtyw and prtyd instructions.
Tested for logical correctness against the prtyw and prtyd instructions
on ppc64le.
Signed-off-by: Matt Brown
---
v2:
- fixed opcodes
- fixed bitshifting and typecast errors
- merged do_prtyw and do_prtyd into single
This adds emulation for the isel instruction.
Tested for correctness against the isel instruction and its extended
mnemonics (lt, gt, eq) on ppc64le.
Signed-off-by: Matt Brown
---
v2:
- fixed opcode
- fixed definition to include the 'if RA=0, a=0' clause
- fixed ccr bitshi
On Wed, 2017-07-19 at 01:44 -0400, Gustavo Romero wrote:
> Currently flush_tmregs_to_thread() does not update accordingly the thread
> structures from live state before a core dump rendering wrong values of
> THFAR, TFIAR, and TEXASR in core dump files.
>
> That commit fixes it by copying from liv
On Fri, 2017-07-21 at 02:34PM, Michael Ellerman wrote:
> -Original Message-
> From: Michael Ellerman [mailto:m...@ellerman.id.au]
> Sent: Friday, July 21, 2017 2:34 PM
> To: Qiang Zhao ; o...@buserror.net
> Cc: valentin.longch...@keymile.com; linuxppc-dev@lists.ozlabs.org; linux-
> ker...
On Sat 7/22/2017 3:34 PM, Dan Carpenter wrote:
> -Original Message-
> From: Dan Carpenter [mailto:dan.carpen...@oracle.com]
> Sent: Saturday, July 22, 2017 3:34 PM
> To: Qiang Zhao
> Cc: Leo Li ; linuxppc-dev@lists.ozlabs.org; kernel-
> janit...@vger.kernel.org
> Subject: [PATCH 1/2] fsl
On Mon, 2017-07-24 at 02:09 +, Qiang Zhao wrote:
> On Fri, 2017-07-21 at 02:34PM, Michael Ellerman wrote:
>
> > -Original Message-
> > From: Michael Ellerman [mailto:m...@ellerman.id.au]
> > Sent: Friday, July 21, 2017 2:34 PM
> > To: Qiang Zhao ; o...@buserror.net
> > Cc: valentin.lo
Signed-off-by: Zhao Qiang
---
Changes for v2:
- include all Errata QE_General4 in #ifdef
drivers/soc/fsl/qe/qe.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/soc/fsl/qe/qe.c b/drivers/soc/fsl/qe/qe.c
index 2ef6fc6..4ac9ce8 100644
--- a/drivers/soc/fsl/qe/qe.c
+++ b/drive
There's a somewhat architectural issue with Radix MMU and KVM.
When coming out of a guest with AIL (ie, MMU enabled), we start
executing hypervisor code with the PID register still containing
whatever the guest has been using.
The problem is that the CPU can (and will) then start prefetching
or s
It's too big to be inline, there is no reason to keep it
that way.
Signed-off-by: Benjamin Herrenschmidt
# Conflicts:
# arch/powerpc/include/asm/mmu_context.h
---
arch/powerpc/include/asm/mmu_context.h | 73 ++
arch/powerpc/mm/Makefile | 2 +-
ar
We open-code testing for the mm being local to the current CPU
in a few places. Use our existing helper instead.
Signed-off-by: Benjamin Herrenschmidt
---
arch/powerpc/mm/hash_utils_64.c | 6 ++
arch/powerpc/mm/hugetlbpage.c| 3 +--
arch/powerpc/mm/pgtable-hash64.c | 4 +---
arch/powerp
It calls switch_mm() which already does the irq save/restore
these days.
Signed-off-by: Benjamin Herrenschmidt
---
arch/powerpc/include/asm/mmu_context.h | 4
1 file changed, 4 deletions(-)
diff --git a/arch/powerpc/include/asm/mmu_context.h
b/arch/powerpc/include/asm/mmu_context.h
index
Makes switch_mm_irqs_off() a bit more readable
Signed-off-by: Benjamin Herrenschmidt
---
arch/powerpc/include/asm/mmu_context.h | 30 ++
1 file changed, 22 insertions(+), 8 deletions(-)
diff --git a/arch/powerpc/include/asm/mmu_context.h
b/arch/powerpc/include/asm/m
Instead of comparing the whole CPU mask every time, let's
keep a counter of how many bits are set in the mask. Thus
testing for a local mm only requires testing if that counter
is 1 and the current CPU bit is set in the mask.
Signed-off-by: Benjamin Herrenschmidt
---
arch/powerpc/include/asm/boo
There is no guarantee that the various isync's involved with
the context switch will order the update of the CPU mask with
the first TLB entry for the new context being loaded by the HW.
Be safe here and add a memory barrier to order any subsequent
load/store which may bring entries into the TLB.
I've realised that changing the arguments for the cacheflush functions
is much more work than its worth, due to other archs using these
functions.
The next patch will just translate the asm cacheflush functions to c,
keeping the existing parameters.
So this won't have any effect on the drivers.
Th
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