On 03/30/2017 05:39 AM, Nicholas Piggin wrote:
> On Tue, 28 Mar 2017 19:15:28 +0530
> Mahesh J Salgaonkar wrote:
>
>> From: Mahesh Salgaonkar
>>
>> For MCE that hit while in use mode MSR(HV=1,PR=1), print the task info on the
>> console MCE error log. This will help to identify application that
On 2017/03/29 10:36PM, Michael Ellerman wrote:
> "Naveen N. Rao" writes:
> > I also tested zram today with the command shared by Wilcox:
> >
> > without patch: 1.493782568 seconds time elapsed( +- 0.08% )
> > with patch: 1.408457577 seconds time elapsed( +- 0.15% )
> >
> >
On Mon, Mar 27, 2017 at 10:43:44PM +1100, Michael Ellerman wrote:
> "Gautham R. Shenoy" writes:
>
> > diff --git a/arch/powerpc/platforms/powernv/idle.c
> > b/arch/powerpc/platforms/powernv/idle.c
> > index 419edff..f335e0f 100644
> > --- a/arch/powerpc/platforms/powernv/idle.c
> > +++ b/arch/po
Fix fallout too.
Signed-off-by: Joe Perches
---
arch/powerpc/platforms/powernv/pci-ioda.c | 31 ---
arch/powerpc/platforms/powernv/pci.h | 2 ++
2 files changed, 18 insertions(+), 15 deletions(-)
diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c
b/arch/po
From: "Aneesh Kumar K.V"
In followup patch we want to increase the va range which will result
in us requiring high_slices to have more than 64 bits. To enable this
convert high_slices to bitmap. We keep the number bits same in this patch
and later change that to higher value
Signed-off-by: Anees
From: "Aneesh Kumar K.V"
This avoid copying the slice_mask struct as function return value
Signed-off-by: Aneesh Kumar K.V
Signed-off-by: Michael Ellerman
---
arch/powerpc/mm/slice.c | 62 ++---
1 file changed, 28 insertions(+), 34 deletions(-)
dif
From: "Aneesh Kumar K.V"
We also update the function arg to struct mm_struct. Move this so that function
finds the definition of struct mm_struct. No functional change in this patch.
Signed-off-by: Aneesh Kumar K.V
Signed-off-by: Michael Ellerman
---
arch/powerpc/include/asm/paca.h | 18 +
From: "Aneesh Kumar K.V"
Remove the checks that TASK_SIZE_USER64 is smaller than H_PGTABLE_RANGE
and USER_VSID_RANGE.
In a following patch we will deliberately add support for a TASK_SIZE
smaller than both ranges, so this will no longer be an error condition.
Signed-off-by: Aneesh Kumar K.V
[m
From: "Aneesh Kumar K.V"
This structure definition need not be in a header since this is used only by
slice.c file. So move it to slice.c. This also allow us to use SLICE_NUM_HIGH
instead of 64.
I also switch the low_slices type to u64 from u16. This doesn't have an impact
on size of struct due
From: "Aneesh Kumar K.V"
We now get output like below which is much better.
[0.935306] good_mask low_slice: 0-15
[0.935360] good_mask high_slice: 0-511
Compared to
[0.953414] good_mask: - 1.
I also fixed an error with slice_dbg printing.
Sig
KVM wants to be able to allocate an MMU context id, which it does
currently by calling __init_new_context().
We're about to rework that code, so provide a wrapper for KVM so it
can not worry about the details.
Signed-off-by: Michael Ellerman
---
arch/powerpc/include/asm/mmu_context.h | 2 +-
a
The min and max context id values used in alloc_context_id() are
currently the right values for use on hash, and happen to also be safe
for use on radix.
But we need to change that in a subsequent patch, so make the min/max
ids parameters and pull the hash values into hsah__alloc_context_id().
Si
Complete the split of the radix vs hash mm context initialisation.
This is mostly code movement, with the exception that we now limit the
context allocation to PRTB_ENTRIES - 1 on radix.
Signed-off-by: Michael Ellerman
---
arch/powerpc/include/asm/book3s/64/mmu.h | 2 +
arch/powerpc/mm/mmu_con
From: "Aneesh Kumar K.V"
Currently we use the top 4 context ids (0x7fffc-0x7) for the kernel.
Kernel VSIDs are built using these top context values and effective the
segement ID. In subsequent patches we want to increase the max effective
address to 512TB. We will achieve that by increasing t
get_kernel_vsid() has a very stern comment saying that it's only valid
for kernel addresses, but there's nothing in the code to enforce that.
Rather than hoping our callers are well behaved, add a check and return
a VSID of 0 (invalid).
Signed-off-by: Michael Ellerman
---
arch/powerpc/include/a
From: "Aneesh Kumar K.V"
Inorder to support large effective address range (512TB), we want to
increase the virtual address bits to 68. But we do have platforms like
p4 and p5 that can only do 65 bit VA. We support those platforms by
limiting context bits on them to 16.
The protovsid -> vsid conv
From: "Aneesh Kumar K.V"
This doesn't have any functional change. But helps in avoiding mistakes
in case the shift bit changes
Signed-off-by: Aneesh Kumar K.V
Signed-off-by: Michael Ellerman
---
arch/powerpc/include/asm/book3s/64/mmu-hash.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-
From: "Aneesh Kumar K.V"
We update the hash linux page table layout such that we can support
512TB. But we limit the TASK_SIZE to 128TB. We can switch to 128TB by
default without conditional because that is the max virtual address
supported by other architectures. We will later add a mechanism to
From: "Aneesh Kumar K.V"
In the followup patch, we will increase the slice array size to handle
512TB range, but will limit the max addr to 128TB. Avoid doing
unnecessary computation and avoid doing slice mask related operation
above address limit.
Signed-off-by: Aneesh Kumar K.V
Signed-off-by:
From: "Aneesh Kumar K.V"
We optmize the slice page size array copy to paca by copying only the
range based on addr_limit. This will require us to not look at page size
array beyond addr_limit in PACA on slb fault. To enable that copy task
size to paca which will be used during slb fault.
Signed-
From: "Aneesh Kumar K.V"
Now that we use all the available virtual address range, we need to make
sure we don't generate VSID such that it overlaps with the reserved vsid
range. Reserved vsid range include the virtual address range used by the
adjunct partition and also the VRMA virtual segment.
From: "Aneesh Kumar K.V"
Signed-off-by: Aneesh Kumar K.V
Signed-off-by: Michael Ellerman
---
arch/powerpc/mm/hugetlbpage-radix.c | 4 ++--
arch/powerpc/mm/mmap.c | 12 ++--
arch/powerpc/mm/slice.c | 6 +++---
arch/powerpc/mm/subpage-prot.c | 3 ++-
4 fi
From: "Aneesh Kumar K.V"
Not all user space application is ready to handle wide addresses. It's known
that
at least some JIT compilers use higher bits in pointers to encode their
information. It collides with valid pointers with 512TB addresses and
leads to crashes.
To mitigate this, we are not
There are some windows in opal entry/exit that can not recover from a
re-entrant interrupt (e.g., machine check) due to using SRR registers,
but they currently do not have MSR_RI clear.
These were found by machine check injection coverage tests using the
powerpc system simulator (Mambo).
Signed-o
Accept the internal delay RGMII variants.
Signed-off-by: Madalin Bucur
---
drivers/net/ethernet/freescale/fman/fman_dtsec.c | 8 +++-
drivers/net/ethernet/freescale/fman/fman_memac.c | 5 -
2 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/freescale/fma
The AVOIDBLOCK flag determines the Tx confirmation queues processing
to be redirected to any available CPU when the current one is slow
in processing them. This may result in a higher Tx confirmation
interrupt count but may reduce pressure on a certain CPU that with
the previous setting would proce
Le 30/03/2017 à 06:44, Andrew Donnellan a écrit :
On 29/03/17 02:14, Christophe Lombard wrote:
This series adds support for a cxl card which supports the Coherent
Accelerator Interface Architecture 2.0.
It requires IBM Power9 system and the Power Service Layer, version 9.
The PSL provides the a
hvc_remove() takes a spin lock first then acquires the console
semaphore. This situation can easily lead to a deadlock scenario
where we call scheduler with spin lock held.
Signed-off-by: Denis Kirjanov
---
drivers/tty/hvc/hvc_console.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
Hi Roy,
On 29/03/17 22:13, Roy Pledge wrote:
> Use the shared-memory-pool mechanism for frame queue descriptor and
> packed frame descriptor record area allocations.
Thanks for persevering with this - in my opinion it's now looking like
it was worth the effort :)
AFAICS the ioremap_wc() that thi
On 2017-03-29 20:08, Tyrel Datwyler wrote:
On 03/29/2017 08:13 AM, Michal Suchánek wrote:
On Wed, 29 Mar 2017 16:51:35 +0200
Greg Kroah-Hartman wrote:
On Wed, Mar 29, 2017 at 02:56:39PM +0200, Michal Suchanek wrote:
While reviewing commit 11c6e16ee13a ("crypto: vmx - Adding asm
subroutines f
Hi Michael,
Any feedback/outlook with this patch ?
Regards,
Vipin
On Friday 10 March 2017 05:27 PM, Vipin K Parashar wrote:
OPAL returns OPAL_WRONG_STATE upon failing to provide
sensor data due to core sleeping/offline. Added check
in opal_get_sensor_data() for sensor read failure with
OPAL_W
In preparation for making the clockevents core NTP correction aware,
all clockevent device drivers must set ->min_delta_ticks and
->max_delta_ticks rather than ->min_delta_ns and ->max_delta_ns: a
clockevent device's rate is going to change dynamically and thus, the
ratio of ns to ticks ceases to s
Sukadev Bhattiprolu [suka...@linux.vnet.ibm.com] wrote:
> Michael Neuling [mi...@neuling.org] wrote:
> > On Thu, 2017-03-16 at 20:33 -0700, Sukadev Bhattiprolu wrote:
> > > Define macros for the VAS hardware registers and bit-fields as well
> > > as couple of data structures needed by the VAS drive
On Mon, Mar 27, 2017 at 09:25:50PM +1100, Benjamin Herrenschmidt wrote:
> On Mon, 2017-03-27 at 21:17 +1100, Michael Ellerman wrote:
> > > If so, is it acceptable to force that kernel to user 64K alignment
> > > even
> > > when it's running on non-PowerNV systems?
> >
> > Probably, but I'm not sur
Currently ppc_md.get_random_seed uses the powernv_get_random_long function.
A guest calling this function would have to go through the hypervisor. The
'darn' instruction, introduced in power 9, allows us to bypass this by
directly obtaining a value from the mmio region.
This patch adds an alternat
On Wed, Mar 22, 2017 at 04:27:50PM -0300, Guilherme G. Piccoli wrote:
> The xmon parameter nobt was added long time ago, by commit 26c8af5f01df
> ("[POWERPC] print backtrace when entering xmon"). The problem that time
> was that during a crash in a machine with USB keyboard, xmon wouldn't
> respond
On Book3s we have two PTE flags used to mark cache-inhibited mappings:
_PAGE_TOLERANT and _PAGE_NON_IDEMPOTENT. Currently the kernel page
table dumper only looks at the generic _PAGE_NO_CACHE which is
defined to be _PAGE_TOLERANT. This patch modifies the dumper so
both flags are shown in the dump.
The current page table dumper scans the linux page tables and coalesces
mappings with adjacent virtual addresses and similar PTE flags. This
behaviour is somewhat broken when you consider the IOREMAP space where
entirely unrelated mappings will appear to be contiguous. This patch
modifies the rang
Nicolai Stange writes:
> In preparation for making the clockevents core NTP correction aware,
> all clockevent device drivers must set ->min_delta_ticks and
> ->max_delta_ticks rather than ->min_delta_ns and ->max_delta_ns: a
> clockevent device's rate is going to change dynamically and thus, the
From: Anton Blanchard
Early on in do_page_fault() we call store_updates_sp(), regardless of
the type of exception. For an instruction miss this doesn't make
sense, because we only use this information to detect if a data miss
is the result of a stack expansion instruction or not.
Worse still, it
Robin Murphy writes:
> Hi Roy,
>
> On 29/03/17 22:13, Roy Pledge wrote:
>> Use the shared-memory-pool mechanism for frame queue descriptor and
>> packed frame descriptor record area allocations.
>
> Thanks for persevering with this - in my opinion it's now looking like
> it was worth the effort :
Add Power9 PVR
Signed-off-by: Sukadev Bhattiprolu
---
arch/powerpc/include/asm/reg.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index fc879fd..7a45ff7 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/a
Power9 introduces a hardware subsystem referred to as the Virtual
Accelerator Switchboard (VAS). VAS allows kernel subsystems and user
space processes to directly access the Nest Accelerator (NX) engines
which implement compression and encryption algorithms in the hardware.
NX has been in Power pr
Define macros for the VAS hardware registers and bit-fields as well
as couple of data structures needed by the VAS driver.
Signed-off-by: Sukadev Bhattiprolu
---
Changelog[v4]
- [Michael Neuling] Move VAS code to arch/powerpc; Reorg vas.h and
vas-internal.h to kernel and uapi ve
Move the GET_FIELD and SET_FIELD macros to vas.h as VAS and other
users of VAS, including NX-842 can use those macros.
There is a lot of related code between the VAS/NX kernel drivers
and skiboot. For consistency switch the order of parameters in
SET_FIELD to match the order in skiboot.
Signed-of
Define some helper functions to access the MMIO regions. We use these
in a follow-on patches to read/write VAS hardware registers. These
helpers are also used to later issue 'paste' instructions to submit
requests to the NX hardware engines.
Signed-off-by: Sukadev Bhattiprolu
---
Changelog [v3]:
Define the vas_rx_win_open() interface. This interface is intended to be
used by the Nest Accelerator (NX) driver(s) to setup receive windows for
one or more NX engines (which implement compression/encryption algorithms
in the hardware).
Follow-on patches will provide an interface to close the win
Implement vas_init() and vas_exit() functions for a new VAS module.
This VAS module is essentially a library for other device drivers
and kernel users of the NX coprocessors like NX-842 and NX-GZIP.
In the future this will be extended to add support for user space
to access the NX coprocessors.
Si
Define helpers to allocate/free VAS window objects. These will
be used in follow-on patches when opening/closing windows.
Signed-off-by: Sukadev Bhattiprolu
---
arch/powerpc/platforms/powernv/vas-window.c | 63 -
1 file changed, 62 insertions(+), 1 deletion(-)
diff -
Define helpers to initialize window context registers of the VAS
hardware. These will be used in follow-on patches when opening/closing
VAS windows.
Signed-off-by: Sukadev Bhattiprolu
---
Changelog[v4]
- Michael Neuling] Use ilog2(), radix_enabled() helpers;
drop warning when 32
Define an interface to open a VAS send window. This interface is
intended to be used the Nest Accelerator (NX) driver(s) to open
a send window and use it to submit compression/encryption requests
to a VAS receive window.
The receive window, identified by the [vasid, cop] parameters, must
already b
Define the vas_win_close() interface which should be used to close a
send or receive windows.
While the hardware configurations required to open send and receive windows
differ, the configuration to close a window is the same for both. So we use
a single interface to close the window.
Signed-off-
Define interfaces (wrappers) to the 'copy' and 'paste' instructions
(which are new in PowerISA 3.0). These are intended to be used to
by NX driver(s) to submit Coprocessor Request Blocks (CRBs) to the
NX hardware engines.
Signed-off-by: Sukadev Bhattiprolu
---
Changelog[v3]
- Map raw CR
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