Add modsw and moduw instruction emulation support to analyse_instr.
modsw is an x-form instruction that calculates signed modulo of values
stored in registers. moduw is similar to modsw but it works with
unsigned values.
Signed-off-by: PrasannaKumar Muralidharan
Reviewed-by: Naveen N. Rao
---
Ch
On 10/12/16 00:32, Gautham R. Shenoy wrote:
> From: "Gautham R. Shenoy"
>
> Currently all the low-power idle states are expected to wake up
> at reset vector 0x100. Which is why the macro IDLE_STATE_ENTER_SEQ
> that puts the CPU to an idle state and never returns.
>
> On ISA_300, when the ESL
On 10/12/16 00:32, Gautham R. Shenoy wrote:
> From: "Gautham R. Shenoy"
>
> In the current code for powernv_add_idle_states, there is a lot of code
> duplication while initializing an idle state in powernv_states table.
>
> Add an inline helper function to populate the powernv_states[] table f
generic hugetlbfs can handle that condition correctly. With HPAGE_SHIFT = 0
we get
[0.241333] hugetlbfs: disabling because there are no supported hugepage sizes
bash-4.2# echo 30 > /proc/sys/vm/nr_hugepages
bash: echo: write error: Operation not supported
Fixes: "powerpc: get hugetlbpage handling
On Tue, 2016-12-13 at 14:28 +1100, Balbir Singh wrote:
> > Also note that there's already a PACA field to "recover" an
> > interrupt
> > snatched by KVM, though it's XICS specific, while your approach is
> > more
> > generic, you may want to merge the two. Talk to Paulus.
> >
>
> That is specific
On Tue, 2016-12-13 at 16:36 +1100, Balbir Singh wrote:
> Yep, although the code works for PPC_XICS only which is good for now.
> When we do XIVE, we can add more bits
We may want to do XIVE differently, dunno. On XIVE we can just poke the
processor priority with a single MMIO store, so we don't ac
truction address: 0xc0054da0
[ 59.089685] Oops: Kernel access of bad area, sig: 11 [#2]
[ 59.089753] SMP NR_CPUS=2048
[ 59.089797] NUMA
[ 59.089817] pSeries
[ 59.089840] Modules linked in:
[ 59.089904] CPU: 1 PID: 3689 Comm: hugepage-mmap Tainted: G D
4.9.
Hi Arnaldo,
Can you please review 2nd and 3rd patch.
-Ravi
On Monday 05 December 2016 09:26 PM, Ravi Bangoria wrote:
> For jump instructions that does not include target address as direct
> operand, show the original disassembled line for them. This is needed
> for certain powerpc jump instructi
Em Mon, Dec 05, 2016 at 09:26:46PM +0530, Ravi Bangoria escreveu:
> +++ b/tools/perf/util/annotate.c
> @@ -223,8 +223,12 @@ bool ins__is_call(const struct ins *ins)
> static int jump__parse(struct arch *arch __maybe_unused, struct ins_operands
> *ops, struct map *map __maybe_unused)
> {
>
Em Mon, Dec 05, 2016 at 09:26:47PM +0530, Ravi Bangoria escreveu:
> If jump target is outside of function range, perf is not handling it
> correctly. Especially when target address is lesser than function start
> address, target offset will be negative. But, target address declared
> to be unsigned
FIX_SRR1() is defined as blank. Last useful instance of FIX_SRR1()
was removed by commit 40ef8cbc6d360 ("powerpc: Get 64-bit configs to
compile with ARCH=powerpc") in 2005.
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/ppc_asm.h | 1 -
arch/powerpc/kernel/entry_32.S | 4
On 12/12/2016 03:07 PM, John Allen wrote:
> Extend the existing PRRN infrastructure to perform the actual affinity
> updating for cpus and memory in addition to the device tree updating. For
> cpus, dynamic affinity updating already appears to exist in the kernel in
> the form of arch_update_cpu_to
This patch set is a first try of implementing some additional
perf events on PPC 8xx.
The first patch of the serie fixes missing MSR RI setting at end of exceptions
The second patch implements the perf counters.
The 8xx has no PMU, however some events can be emulated by other means.
This patch i
At exception prologs, once SRR0 and SRR1 have been saved, MSR RI is
set to mark the interrupt as recoverable.
MSR RI has to be unset before writing into SRR0 and SRR1 at exception
epilogs.
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/ppc_asm.h | 6 ++
arch/powerpc/include/as
The 8xx has no PMU, however some events can be emulated by other means.
This patch implements the following 4 events:
cpu-cycles OR cycles [Hardware event]
instructions [Hardware event]
dTLB-load-misses
ea, sig: 11 [#2]
> [ 59.089753] SMP NR_CPUS=2048
> [ 59.089797] NUMA
> [ 59.089817] pSeries
> [ 59.089840] Modules linked in:
> [ 59.089904] CPU: 1 PID: 3689 Comm: hugepage-mmap Tainted: G D
> 4.9.0-next-20161213-11823-gff9fa2f-dirty #6
> [ 59.09
On Tue, Dec 13, 2016 at 07:19:41PM +0100, Christophe Leroy wrote:
> At exception prologs, once SRR0 and SRR1 have been saved, MSR RI is
> set to mark the interrupt as recoverable.
>
> MSR RI has to be unset before writing into SRR0 and SRR1 at exception
> epilogs.
Why? What goes wrong without th
Le 13/12/2016 à 20:15, Segher Boessenkool a écrit :
On Tue, Dec 13, 2016 at 07:19:41PM +0100, Christophe Leroy wrote:
At exception prologs, once SRR0 and SRR1 have been saved, MSR RI is
set to mark the interrupt as recoverable.
MSR RI has to be unset before writing into SRR0 and SRR1 at except
On Tue, Dec 13, 2016 at 09:39:55PM +0100, christophe leroy wrote:
> Le 13/12/2016 à 20:15, Segher Boessenkool a écrit :
> >On Tue, Dec 13, 2016 at 07:19:41PM +0100, Christophe Leroy wrote:
> >>At exception prologs, once SRR0 and SRR1 have been saved, MSR RI is
> >>set to mark the interrupt as recov
On 10/12/16 00:32, Gautham R. Shenoy wrote:
> From: "Gautham R. Shenoy"
>
> The power9_idle_stop method currently takes only the requested stop
> level as a parameter and picks up the rest of the PSSCR bits from a
> hand-coded macro. This is not a very flexible design, especially when
> the fir
On 14/12/16 02:27, Benjamin Herrenschmidt wrote:
> On Tue, 2016-12-13 at 16:36 +1100, Balbir Singh wrote:
>> Yep, although the code works for PPC_XICS only which is good for now.
>> When we do XIVE, we can add more bits
>
> We may want to do XIVE differently, dunno. On XIVE we can just poke the
POWER9 contains an off core mmu called the nest mmu (NMMU). This is
used by other hardware units on the chip to translate virtual
addresses into real addresses. The unit attempting an address
translation provides the majority of the context required for the
translation request except for the base a
On Wed, Oct 26, 2016 at 8:51 PM, Michael Ellerman
wrote:
> On Thu, 2016-06-10 at 13:42:19 UTC, Segher Boessenkool wrote:
>> PowerPC's "cmp" instruction has four operands. Normally people write
>> "cmpw" or "cmpd" for the second cmp operand 0 or 1. But, frequently
>> people forget, and write "cmp
On 10/12/16 02:35, Alex Williamson wrote:
> On Fri, 9 Dec 2016 18:53:43 +1100
> Alexey Kardashevskiy wrote:
>
>> On 09/12/16 04:55, Alex Williamson wrote:
>>> On Thu, 8 Dec 2016 19:19:56 +1100
>>> Alexey Kardashevskiy wrote:
>>>
This allows the host kernel to handle H_PUT_TCE, H_PUT_TCE
On Wed, Dec 14, 2016 at 02:01:50PM +1030, Joel Stanley wrote:
> >> With older binutils this is silently accepted as if this was "cmpw",
> >> while often "cmpd" is wanted. With newer binutils GAS will complain
> >> about this for 64-bit code. For 32-bit code it still silently assumes
> >> "cmpw" i
For transparent hugepage config, we need to use double the size
of the pmd. Hence we should use PMD_CACHE_INDEX when allocating
pagetable cache. For all configs other than book3s 64k this value
is same as PMD_INDEX_SIZE. With 4k, since we don't support
transparent hugepage in hash mode, we can use
When we switched to big endian page table, we never updated
the hugepd format such that it can work for both big endian and
little endian config. This patch series update hugepd format
such that it is looked at as __be64 value in big endian page
table config.
This patch also switch hugepd_t.pd fro
We don't do this for other page table entries. So lets keep this simple
and always return false for hugepd check on a 64K page size config.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/pgtable-64k.h | 5 -
arch/powerpc/mm/hugetlbpage-hash64.c | 21 -
Hi Balbir,
On Tue, Dec 13, 2016 at 09:13:26PM +1100, Balbir Singh wrote:
>
>
> On 10/12/16 00:32, Gautham R. Shenoy wrote:
> > From: "Gautham R. Shenoy"
> > diff --git a/arch/powerpc/include/asm/cpuidle.h
> > b/arch/powerpc/include/asm/cpuidle.h
> > index 3919332..0a3255b 100644
> > --- a/arch
Hi Balbir,
On Tue, Dec 13, 2016 at 10:51:04PM +1100, Balbir Singh wrote:
>
>
> On 10/12/16 00:32, Gautham R. Shenoy wrote:
> > From: "Gautham R. Shenoy"
> >
> > In the current code for powernv_add_idle_states, there is a lot of code
> > duplication while initializing an idle state in powernv_s
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