Signed-off-by: jun
---
drivers/iommu/fsl_pamu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/iommu/fsl_pamu.c b/drivers/iommu/fsl_pamu.c
index db3a1cd..a8fe503 100644
--- a/drivers/iommu/fsl_pamu.c
+++ b/drivers/iommu/fsl_pamu.c
@@ -668,7 +668,7 @@ static bool has_e
On Fri, 2016-21-10 at 09:03:05 UTC, Paul Mackerras wrote:
> Commit 8117ac6a6c2f ("powerpc/powernv: Switch off MMU before entering
> nap/sleep/rvwinkle mode", 2014-12-10) fixed a race condition where one
> thread entering a KVM guest could switch the MMU context to the guest
> while another thread w
On Fri, 2016-21-10 at 09:04:17 UTC, Paul Mackerras wrote:
> This fixes a race condition where one thread that is entering or
> leaving a power-saving state can inadvertently ignore the lock bit
> that was set by another thread, and potentially also clear it.
> The core_idle_lock_held function is ca
On Fri, 2016-21-10 at 09:23:53 UTC, Vaibhav Jain wrote:
> In some error paths in functions cxl_start_context and
> afu_ioctl_start_work pid references to the current & group-leader tasks
> can leak after they are taken. This patch fixes these error paths to
> release these pid references before exi
On Thu, 2016-20-10 at 03:57:12 UTC, Michael Ellerman wrote:
> Commit 5d375199ea96 ("KVM: PPC: Book3S HV: Set server for passed-through
> interrupts") broke the SMP=n build:
>
> arch/powerpc/kvm/book3s_hv_rm_xics.c:758:2: error: implicit declaration of
> function 'get_hard_smp_processor_id'
>
>
On Thu, 2016-06-10 at 13:42:19 UTC, Segher Boessenkool wrote:
> PowerPC's "cmp" instruction has four operands. Normally people write
> "cmpw" or "cmpd" for the second cmp operand 0 or 1. But, frequently
> people forget, and write "cmp" with just three operands.
>
> With older binutils this is si
Valentin Rothberg writes:
> On Wed, Oct 26, 2016 at 7:52 AM, Michael Ellerman wrote:
>> Cyril Bur writes:
>>
>>> On Wed, 2016-10-05 at 07:57 +0200, Valentin Rothberg wrote:
s/ALIVEC/ALTIVEC/
>>>
>>> Oops, nice catch
>>>
Signed-off-by: Valentin Rothberg
>>>
>>> Reviewed-by: Cyril
On Wed, Oct 26, 2016 at 12:40 PM, Michael Ellerman wrote:
> Valentin Rothberg writes:
>
>> On Wed, Oct 26, 2016 at 7:52 AM, Michael Ellerman
>> wrote:
>>> Cyril Bur writes:
>>>
On Wed, 2016-10-05 at 07:57 +0200, Valentin Rothberg wrote:
> s/ALIVEC/ALTIVEC/
>
Oops, nice c
Reza Arbab writes:
> On Wed, Oct 26, 2016 at 09:34:18AM +1100, Balbir Singh wrote:
>>I still believe we need your changes, I was wondering if we've tested
>>it against normal memory nodes and checked if any memblock
>>allocations end up there. Michael showed me some memblock
>>allocations on node
From: Simon Guo
This selftest suite is for PPC register ptrace functionality. It
is also useful for Transaction Memory functionality verification.
Signed-off-by: Anshuman Khandual
Signed-off-by: Simon Guo
Test Result (All tests pass on both BE and LE)
From: Anshuman Khandual
This patch adds SPR number for TAR, PPR, DSCR special
purpose registers. It also adds TM, VSX, VMX related
instructions which will then be used by patches later
in the series.
Now that the new DSCR register definitions (SPRN_DSCR_PRIV and
SPRN_DSCR) are defined outside th
From: Simon Guo
There are some functions, especially register related, which can
be shared across multiple selftests/powerpc test directories.
This patch creates a new utility directory to store those shared
functionalities, so that the file layout becomes more neat.
Signed-off-by: Simon Guo
-
From: Anshuman Khandual
This patch adds ptrace interface test for EBB/PMU specific
registers. This also adds some generic ptrace interface
based helper functions to be used by other patches later
on in the series.
Signed-off-by: Anshuman Khandual
Signed-off-by: Simon Guo
---
tools/testing/sel
From: Anshuman Khandual
This patch adds ptrace interface test for GPR/FPR registers.
This adds ptrace interface based helper functions related to
GPR/FPR access and some assembly helper functions related to
GPR/FPR registers.
Signed-off-by: Anshuman Khandual
Signed-off-by: Simon Guo
---
tools
From: Anshuman Khandual
This patch adds ptrace interface test for GPR/FPR registers
inside TM context. This adds ptrace interface based helper
functions related to checkpointed GPR/FPR access.
Signed-off-by: Anshuman Khandual
Signed-off-by: Simon Guo
---
tools/testing/selftests/powerpc/ptrace
From: Anshuman Khandual
This patch adds ptrace interface test for GPR/FPR registers
inside suspended TM context.
Signed-off-by: Anshuman Khandual
Signed-off-by: Simon Guo
---
tools/testing/selftests/powerpc/ptrace/Makefile| 2 +-
.../selftests/powerpc/ptrace/ptrace-tm-spd-gpr.c | 169
From: Anshuman Khandual
This patch adds ptrace interface test for TAR, PPR, DSCR
registers. This also adds ptrace interface based helper
functions related to TAR, PPR, DSCR register access.
Signed-off-by: Anshuman Khandual
Signed-off-by: Simon Guo
---
tools/testing/selftests/powerpc/ptrace/Ma
From: Anshuman Khandual
This patch adds ptrace interface test for TAR, PPR, DSCR
registers inside TM context. This also adds ptrace
interface based helper functions related to checkpointed
TAR, PPR, DSCR register access.
Signed-off-by: Anshuman Khandual
Signed-off-by: Simon Guo
---
tools/test
From: Anshuman Khandual
This patch adds ptrace interface test for TAR, PPR, DSCR
registers inside suspended TM context.
Signed-off-by: Anshuman Khandual
Signed-off-by: Simon Guo
---
tools/testing/selftests/powerpc/ptrace/Makefile| 2 +-
.../selftests/powerpc/ptrace/ptrace-tm-spd-tar.c
From: Anshuman Khandual
This patch adds ptrace interface test for VSX, VMX registers.
This also adds ptrace interface based helper functions related
to VSX, VMX registers access. This also adds some assembly
helper functions related to VSX and VMX registers.
Signed-off-by: Anshuman Khandual
Sig
From: Anshuman Khandual
This patch adds ptrace interface test for VSX, VMX registers
inside TM context. This also adds ptrace interface based helper
functions related to chckpointed VSX, VMX registers access.
Signed-off-by: Anshuman Khandual
Signed-off-by: Simon Guo
---
tools/testing/selftest
From: Anshuman Khandual
This patch adds ptrace interface test for VSX, VMX registers
inside suspended TM context.
Signed-off-by: Anshuman Khandual
Signed-off-by: Simon Guo
---
tools/testing/selftests/powerpc/ptrace/Makefile| 3 +-
.../selftests/powerpc/ptrace/ptrace-tm-spd-vsx.c | 185
From: Anshuman Khandual
This patch adds ptrace interface test for TM SPR registers. This
also adds ptrace interface based helper functions related to TM
SPR registers access.
Signed-off-by: Anshuman Khandual
Signed-off-by: Simon Guo
---
tools/testing/selftests/powerpc/ptrace/Makefile| 3
From: Anshuman Khandual
This patch adds a .gitignore file for all the executables in
the ptrace test directory thus making invisible with git status
query.
Signed-off-by: Anshuman Khandual
Signed-off-by: Simon Guo
---
tools/testing/selftests/powerpc/ptrace/.gitignore | 11 +++
1 file
From: Anshuman Khandual
Fixes the following build failure -
cp_abort.c:90:3: error: ‘for’ loop initial declarations are only
allowed in C99 or C11 mode
for (int i = 0; i < NUM_LOOPS; i++) {
^
cp_abort.c:90:3: note: use option -std=c99, -std=gnu99, -std=c11 or
-std=gnu11 to compile your cod
Someone was just mentioning in another thread that removing the check
from iounmap() is not portable to other arches and then I remembered
that Markus removed a bunch of these.
We should consider reverting this, perhaps?
regards,
dan carpenter
On Sun, Jan 04, 2015 at 02:36:01PM +0100, SF Markus
On Wed, 2016-10-26 at 15:26 +0300, Dan Carpenter wrote:
> Someone was just mentioning in another thread that removing the check
> from iounmap() is not portable to other arches and then I remembered
> that Markus removed a bunch of these.
>
> We should consider reverting this, perhaps?
Can't we t
On Wed, Oct 26, 2016 at 02:28:59PM +0200, Johannes Berg wrote:
> On Wed, 2016-10-26 at 15:26 +0300, Dan Carpenter wrote:
> > Someone was just mentioning in another thread that removing the check
> > from iounmap() is not portable to other arches and then I remembered
> > that Markus removed a bunch
Hello Matthias Fuchs,
The patch 2af59f7d5c3e: "[POWERPC] 4xx: Add 405GPr and 405EP support
in boot wrapper" from Dec 7, 2007, leads to the following static
checker warning:
arch/powerpc/boot/4xx.c:567 ibm405gp_fixup_clocks()
warn: mask and shift to zero
arch/powerpc/boot/4xx.c
On Wed, Oct 26, 2016 at 09:52:53PM +1100, Michael Ellerman wrote:
As far as I know, power has nothing like the SRAT that tells us, at
boot, which memory is hotpluggable.
On pseries we have the ibm,dynamic-memory device tree property, which
can contain ranges of memory that are not yet "assigned
On Wed, 2016-09-21 at 14:57 +0800, Yangbo Lu wrote:
> diff --git a/drivers/soc/fsl/Kconfig b/drivers/soc/fsl/Kconfig
> new file mode 100644
> index 000..b99764c
> --- /dev/null
> +++ b/drivers/soc/fsl/Kconfig
> @@ -0,0 +1,19 @@
> +#
> +# Freescale SOC drivers
> +#
> +
> +source "drivers/soc/fsl
On Wed, 2016-10-26 at 16:03 +0300, Dan Carpenter wrote:
> 565 cbdv = ((pllmr & 0x0006) >> 17) + 1; /* CPU:PLB */
> 566 opdv = ((pllmr & 0x00018000) >> 15) + 1; /* PLB:OPB */
> 567 ppdv = ((pllmr & 0x1800) >> 13) + 1; /* PLB:PCI */
>
On Wed, Oct 26, 2016 at 01:57:23PM -0500, Benjamin Herrenschmidt wrote:
> On Wed, 2016-10-26 at 16:03 +0300, Dan Carpenter wrote:
> > 565 cbdv = ((pllmr & 0x0006) >> 17) + 1; /* CPU:PLB */
> > 566 opdv = ((pllmr & 0x00018000) >> 15) + 1; /* PLB:OPB */
> > 567
On Wed, 2016-10-26 at 22:07 +0300, Dan Carpenter wrote:
> On Wed, Oct 26, 2016 at 01:57:23PM -0500, Benjamin Herrenschmidt
> wrote:
> >
> > On Wed, 2016-10-26 at 16:03 +0300, Dan Carpenter wrote:
> > >
> > > 565 cbdv = ((pllmr & 0x0006) >> 17) + 1; /*
> > > CPU:PLB */
> > > 566
Valentin Rothberg writes:
> On Wed, Oct 26, 2016 at 12:40 PM, Michael Ellerman
> wrote:
>> diff --git a/scripts/checkkconfigsymbols.py b/scripts/checkkconfigsymbols.py
>> index a32e4da4c117..3820f00b066a 100755
>> --- a/scripts/checkkconfigsymbols.py
>> +++ b/scripts/checkkconfigsymbols.py
>> @@
On Wed, 2016-10-26 at 16:52 +1100, Michael Ellerman wrote:
> Cyril Bur writes:
>
> > On Wed, 2016-10-05 at 07:57 +0200, Valentin Rothberg wrote:
> > > s/ALIVEC/ALTIVEC/
> > >
> >
> > Oops, nice catch
> >
> > > Signed-off-by: Valentin Rothberg
> >
> > Reviewed-by: Cyril Bur
>
> How did we n
Hi Scott,
> -Original Message-
> From: Scott Wood [mailto:o...@buserror.net]
> Sent: Thursday, October 27, 2016 1:06 AM
> To: Y.B. Lu; linux-...@vger.kernel.org; ulf.hans...@linaro.org; Arnd
> Bergmann
> Cc: linuxppc-dev@lists.ozlabs.org; devicet...@vger.kernel.org; linux-arm-
> ker...@li
Version v3.00 of the ISA added a new compat level to the processor
compatibility register (PCR), an ISA v2.07 compatibility mode.
Upstream QEMU already supports this so it may as well go into the kernel
now.
Suraj Jitindar Singh (2):
powerpc: Define new ISA v3.00 logical PVR value and PCR regis
ISA 3.00 adds the logical PVR value 0x0f05, so add a definition for
this.
Define PCR_ARCH_207 to reflect ISA 2.07 compatibility mode in the processor
compatibility register (PCR).
Signed-off-by: Suraj Jitindar Singh
---
arch/powerpc/include/asm/reg.h | 2 ++
1 file changed, 2 insertions(+)
The function kvmppc_set_arch_compat() is used to determine the value of the
processor compatibility register (PCR) for a guest running in a given
compatibility mode. There is currently no support for v3.00 of the ISA.
Add support for v3.00 of the ISA which adds an ISA v2.07 compatilibity mode
to t
On 10/01/2016 04:11 PM, Anton Blanchard wrote:
> From: Anton Blanchard
>
> An hcall was recently added that does exactly what we need
> during kexec - it clears the entire MMU hash table, ignoring any
> VRMA mappings.
>
> Try it and fall back to the old method if we get a failure.
>
> On a POWE
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