From: "Naveen N. Rao"
Date: Sat, 24 Sep 2016 02:10:04 +0530
> These samples fail to compile as 'struct flow_keys' conflicts with
> definition in net/flow_dissector.h. Fix the same by renaming the
> structure used in the sample.
>
> Signed-off-by: Naveen N. Rao
Applied to net-next.
From: "Naveen N. Rao"
Date: Sat, 24 Sep 2016 02:10:05 +0530
> seccomp_phase1() does not exist anymore. Instead, update sample to use
> __seccomp_filter(). While at it, set max locked memory to unlimited.
>
> Signed-off-by: Naveen N. Rao
Also applied to net-next, thanks.
- Original Message -
> From: "Herbert Xu"
> To: "Marcelo Cerri"
> Cc: "Jan Stancek" , "rui y wang" ,
> mhce...@linux.vnet.ibm.com,
> leosi...@linux.vnet.ibm.com, pfsmor...@linux.vnet.ibm.com,
> linux-cry...@vger.kernel.org,
> linuxppc-dev@lists.ozlabs.org, linux-ker...@vger.kernel.o
From: Scott Wood
Sent: Sunday, September 25, 2016 3:24 PM
To: C.H. Zhao
Cc: linuxppc-dev@lists.ozlabs.org; linux-ker...@vger.kernel.org;
z.chen...@gmail.com; Jason Jin
Subject: Re: [v3,4/5] powerpc/pm: support deep sleep feature on T104x
On Tue, Aug 02, 2016 at 07:59:31PM +0800, Chenhui Zha
Hi,
On Tue, Sep 27, 2016 at 05:01:03AM -0400, Jan Stancek wrote:
> So, if we extended p8_ghash_desc_ctx to accommodate fallback_desc's ctx
> and then provided statesize/import/export, would that be acceptable?
>
> struct p8_ghash_desc_ctx {
> ...
> struct shash_desc fallback_desc;
Em Thu, Sep 15, 2016 at 03:24:40PM -0700, Sukadev Bhattiprolu escreveu:
> At run time (when 'perf' is starting up), locate the specific table
> of PMU events that corresponds to the current CPU. Using that table,
> create aliases for the each of the PMU events in the CPU. The use
> these aliases to
From: Anton Blanchard
Pull in a version of Anton's null_syscall benchmark:
http://ozlabs.org/~anton/junkcode/null_syscall.c
Into tools/testing/selftests/powerpc/benchmarks.
Suggested-by: Michael Ellerman
Signed-off-by: Anton Blanchard
Signed-off-by: Rui Teng
---
.../testing/selftests/powerpc
On Mon, Sep 26, 2016 at 09:59:54AM -0700, Andi Kleen wrote:
> On Mon, Sep 26, 2016 at 12:03:43PM -0300, Arnaldo Carvalho de Melo wrote:
> > Em Mon, Sep 26, 2016 at 10:35:33AM +0200, Jiri Olsa escreveu:
> > > ping.. is that working for you? IMO we can include this
> > > as additional patch to the se
Hello,
Any updates?
Arnaldo, if patches looks good to you, can you please pickup them.
-Ravi
On Wednesday 21 September 2016 09:17 PM, Ravi Bangoria wrote:
> Currently Perf annotate support code navigation (branches and calls)
> only when run on the same architecture where perf.data was recorded
Use the more common logging mechanism.
Miscellanea:
o Realign multiline statements
o Coalesce format
Signed-off-by: Joe Perches
---
drivers/usb/gadget/function/rndis.c | 9 -
drivers/usb/gadget/function/u_serial.c | 4 ++--
drivers/usb/gadget/udc/at91_udc.h | 2 +-
driver
Joe Perches writes:
> Use the more common logging mechanism.
>
> Miscellanea:
>
> o Realign multiline statements
> o Coalesce format
>
> Signed-off-by: Joe Perches
For pxa25x_udc.h:
Acked-by: Robert Jarzmik
Cheers.
--
Robert
Em Thu, Sep 15, 2016 at 03:24:43PM -0700, Sukadev Bhattiprolu escreveu:
> From: Andi Kleen
>
> Add support to print alias descriptions in perf list, which
> are taken from the generated event files.
>
> The sorting code is changed to put the events with descriptions
> at the end. The description
Hi Michael,
Here is the link to the bug raised on launchpad.
https://bugs.launchpad.net/ubuntu/+source/gcc-5/+bug/1628207
On 09/23/2016 09:45 AM, Akshay Adiga wrote:
Hi Michael,
Anton found this bug and raised it against gcc v7.0 and a fix is
available
in upstream gcc.
https://gcc.gnu
Arnaldo Carvalho de Melo [a...@kernel.org] wrote:
> Em Thu, Sep 15, 2016 at 03:24:43PM -0700, Sukadev Bhattiprolu escreveu:
> > From: Andi Kleen
> >
> > Add support to print alias descriptions in perf list, which
> > are taken from the generated event files.
> >
> > The sorting code is changed t
On Sun, 25 Sep 2016 21:36:59 +1000
Anton Blanchard wrote:
> Hi Nick,
>
> > Hmm. If we execute this loop once, we'll only fetch additional nops.
> > Twice, and we make up for them by not fetching unused instructions.
> > More than twice and we may start winning.
> >
> > For large sizes it probab
Hi Gavin,
On Mon, Sep 19, 2016 at 09:53:30AM +1000, Gavin Shan wrote:
> In pci_update_resource(), the PCI device's memory decoding (0x2 in
> PCI_COMMAND) is disabled when 64-bits memory BAR is updated if the
> PCI device's memory space wasn't asked to be always on by @pdev->
> mmio_always_on. The
Jan,
Can you check if the problem occurs with this patch?
---
drivers/crypto/vmx/ghash.c | 28 +---
drivers/crypto/vmx/vmx.c | 9 +
2 files changed, 26 insertions(+), 11 deletions(-)
diff --git a/drivers/crypto/vmx/ghash.c b/drivers/crypto/vmx/ghash.c
index 6
On Tue, 2016-09-27 at 14:20 -0500, Bjorn Helgaas wrote:
> On Mon, Sep 19, 2016 at 09:53:30AM +1000, Gavin Shan wrote:
> > In pci_update_resource(), the PCI device's memory decoding (0x2 in
> > PCI_COMMAND) is disabled when 64-bits memory BAR is updated if the
> > PCI device's memory space wasn't as
Highlights include qbman support (a prerequisite for datapath drivers
such as ethernet), a PCI DMA fix+improvement, reset handler changes, more
8xx optimizations, and some cleanups and fixes.
The following changes since commit f1a55ce0544251746d9b52fb85ad32f31a43fbd2:
powerpc: Clean up tm_abort
The top 3 bits of the lower order byte should contain the
AP encoding, we assume the top 3 bits of the MSB.
Signed-off-by: Balbir Singh
---
- Detected while reviewing Chris Smart's patch to add radix-AP-encoding
to skiboot
- Also fixed typo (sift/shift)
arch/powerpc/mm/pgtable-radix.c |
On Wed, Sep 28, 2016 at 07:45:32AM +1000, Benjamin Herrenschmidt wrote:
>On Tue, 2016-09-27 at 14:20 -0500, Bjorn Helgaas wrote:
>> On Mon, Sep 19, 2016 at 09:53:30AM +1000, Gavin Shan wrote:
>> > In pci_update_resource(), the PCI device's memory decoding (0x2 in
>> > PCI_COMMAND) is disabled when
On Wed, 2016-09-28 at 09:37 +1000, Gavin Shan wrote:
>
> Yeah, it's safe to update it with memory decoding on. As the function call
> flow I listed in the changelog (as below), nobody should access the IOV BAR
> when pci_update_resource() is called. However, the PF's memory BARs might
> be accesse
On Wed, Sep 28, 2016 at 10:06:44AM +1000, Benjamin Herrenschmidt wrote:
>On Wed, 2016-09-28 at 09:37 +1000, Gavin Shan wrote:
>>
>> Yeah, it's safe to update it with memory decoding on. As the function call
>> flow I listed in the changelog (as below), nobody should access the IOV BAR
>> when pci_
Denys Vlasenko writes:
> On 32-bit powerpc the ELF PLT sections of binaries (built with --bss-plt,
> or with a toolchain which defaults to it) look like this:
Or (it seems), for all programs built with -pg (profiling).
> [17] .sbss NOBITS 0002aff8 01aff8 14 00 WA 0
Balbir Singh writes:
> The top 3 bits of the lower order byte should contain the
> AP encoding, we assume the top 3 bits of the MSB.
Are you sure, Power architecture documents always confuse about MSB vs
lowe order bytes. ?
>
> Signed-off-by: Balbir Singh
> ---
>
> - Detected while reviewing
On Tue, Sep 27, 2016 at 05:01:03AM -0400, Jan Stancek wrote:
>
> Also, does that mean that padlock_sha has similar problem?
> It does not seem to reserve any space for fallback __ctx and it calls
> init()/update()/export() with padlock_sha_desc's fallback:
>
> struct padlock_sha_desc {
>
On Tue, Sep 27, 2016 at 04:46:44PM -0300, Marcelo Cerri wrote:
>
> Can you check if the problem occurs with this patch?
In light of the fact that padlock-sha is the correct example
to follow, you only need to add one line to the init_tfm fucntion
to update the descsize based on that of the fallba
QE was supported on PowerPC, and dependent on PPC,
Now it is supported on other platforms. so remove PPCisms.
Signed-off-by: Zhao Qiang
---
Changes for v2:
- na
Changes for v3:
- add NO_IRQ
Changes for v4:
- modify spin_event_timeout to opencoded timeout loop
- rem
On Wed, Sep 28, 2016 at 11:42:11AM +1000, Michael Ellerman wrote:
> But this is not really a powerpc patch, and I'm not an ELF expert. So
> I'm not comfortable merging it via the powerpc tree. It doesn't look
> like we really have a maintainer for binfmt_elf.c, so I'm not sure who
> should be acki
move the driver from drivers/soc/fsl/qe to drivers/irqchip,
merge qe_ic.h and qe_ic.c into irq-qeic.c.
Signed-off-by: Zhao Qiang
---
Changes for v2:
- modify the subject and commit msg
Changes for v3:
- merge .h file to .c, rename it with irq-qeic.c
Changes for v4:
- modif
The codes of qe_ic init from a variety of platforms are redundant,
merge them to a common function and put it to irqchip/irq-qeic.c
For non-p1021_mds mpc85xx_mds boards, use "qe_ic_init(np, 0,
qe_ic_cascade_low_mpic, qe_ic_cascade_high_mpic);" instead of
"qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic
qeic_of_init just get device_node of qeic from dtb and call qe_ic_init,
pass the device_node to qe_ic_init.
So merge qeic_of_init into qe_ic_init to get the qeic node in
qe_ic_init.
Signed-off-by: Zhao Qiang
---
Changes for v2:
- modify subject and commit msg
- return 0 and add pu
QEIC was supported on PowerPC, and dependent on PPC,
Now it is supported on other platforms, so remove PPCisms.
Signed-off-by: Zhao Qiang
---
Changes for v6:
- new added
drivers/irqchip/irq-qeic.c | 28 +---
include/soc/fsl/qe/qe_ic.h | 12 ++--
2 files c
On Mon, Sep 26, 2016 at 10:56:07PM +1000, Gavin Shan wrote:
>This supports PCI surprise hotplug. The design is highlighted as
>below:
>
> * The PCI slot's surprise hotplug capability is exposed through
> device node property "ibm,slot-surprise-pluggable", meaning
> PCI surprise hotplug wi
This series of patches supports PCI surprise hotplug on PowerNV platform.
Without the corresponding skiboot patches, this feature won't be enabled
and workable.
* The skiboot patches can be found in below link (PATCH[01/16):
https://patchwork.ozlabs.org/project/skiboot/list/?submitter=6392
Function eeh_pe_set_option() is used to apply the requested options
(enable, disable, unfreeze) in EEH virtualization path. The semantics
of this function isn't complete until freezing is supported.
This allows to freeze the indicated PE. The new semantics is going to
be used in PCI surprise hot r
This exports @confirm_error_lock so that eeh_serialize_{lock, unlock}()
can be used to freeze the affected PE in PCI surprise hot remove path.
Signed-off-by: Gavin Shan
---
arch/powerpc/kernel/eeh.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/powerpc/kernel/eeh.c b/arch/powerpc/kern
This removes likely() and unlikely() in pnv_php.c as the code isn't
running in hot path. Those macros to affect CPU's branch stream don't
help a lot for performance. I used them to identify the cases are
likely or unlikely to happen. No logical changes introduced.
Signed-off-by: Gavin Shan
---
d
This unfreezes PE when it's initialized because the PE might be put
into frozen state in the last hot remove path. It's not harmful to
do so if the PE is already in unfrozen state.
Signed-off-by: Gavin Shan
---
arch/powerpc/platforms/powernv/pci-ioda.c | 12
1 file changed, 12 inser
This exports eeh_pe_state_mark(). It will be used to mark the surprise
hot removed PE as isolated to avoid unexpected EEH error reporting in
surprise remove path.
Signed-off-by: Gavin Shan
---
arch/powerpc/kernel/eeh_pe.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/powerpc/kernel/ee
This supports PCI surprise hotplug. The design is highlighted as
below:
* The PCI slot's surprise hotplug capability is exposed through
device node property "ibm,slot-surprise-pluggable", meaning
PCI surprise hotplug will be disabled if skiboot doesn't support
it yet.
* The in
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