On Wed, Jul 13, 2016 at 02:59:51PM +1000, Stewart Smith wrote:
> Russell King - ARM Linux writes:
> > On Tue, Jul 12, 2016 at 10:58:05PM +0200, Petr Tesarik wrote:
> >> I'm not an expert on DTB, so I can't provide an example of code
> >> execution, but you have already mentioned the /chosen/linux,
Arnaldo Carvalho de Melo writes:
> Em Tue, Jul 12, 2016 at 07:51:46AM +0530, Ravi Bangoria escreveu:
>> Hi Arnaldo,
>>
>> On Friday 08 July 2016 02:01 PM, Michael Ellerman wrote:
>> > Ravi Bangoria writes:
>> >
>> > > On Wednesday 06 July 2016 03:38 PM, Michael Ellerman wrote:
>> > >
>> > > I
On 13 July 2016 at 09:36, Russell King - ARM Linux
wrote:
> On Wed, Jul 13, 2016 at 02:59:51PM +1000, Stewart Smith wrote:
>> Russell King - ARM Linux writes:
>> > On Tue, Jul 12, 2016 at 10:58:05PM +0200, Petr Tesarik wrote:
>> >> I'm not an expert on DTB, so I can't provide an example of code
>
Russell King - ARM Linux writes:
> On Wed, Jul 13, 2016 at 02:59:51PM +1000, Stewart Smith wrote:
>> Russell King - ARM Linux writes:
>> > On Tue, Jul 12, 2016 at 10:58:05PM +0200, Petr Tesarik wrote:
>> >> I'm not an expert on DTB, so I can't provide an example of code
>> >> execution, but you h
On Wednesday, July 13, 2016 10:36:14 AM CEST Dave Young wrote:
> On 07/12/16 at 03:50pm, Mark Rutland wrote:
> > On Tue, Jul 12, 2016 at 04:24:10PM +0200, Arnd Bergmann wrote:
> > > On Tuesday, July 12, 2016 10:18:11 AM CEST Vivek Goyal wrote:
> >
> > /proc/devicetree (aka /sys/firmware/devicetree
On Wed, Jul 13, 2016 at 09:47:56AM +0200, Ard Biesheuvel wrote:
> On 13 July 2016 at 09:36, Russell King - ARM Linux
> wrote:
> > On Wed, Jul 13, 2016 at 02:59:51PM +1000, Stewart Smith wrote:
> >> Russell King - ARM Linux writes:
> >> > On Tue, Jul 12, 2016 at 10:58:05PM +0200, Petr Tesarik wrot
Ard Biesheuvel writes:
> On 13 July 2016 at 09:36, Russell King - ARM Linux
> wrote:
>> On Wed, Jul 13, 2016 at 02:59:51PM +1000, Stewart Smith wrote:
>>> Russell King - ARM Linux writes:
>>> > On Tue, Jul 12, 2016 at 10:58:05PM +0200, Petr Tesarik wrote:
>>> >> I'm not an expert on DTB, so I ca
Arnd Bergmann writes:
> On Wednesday, July 13, 2016 10:36:14 AM CEST Dave Young wrote:
>> On 07/12/16 at 03:50pm, Mark Rutland wrote:
>> > On Tue, Jul 12, 2016 at 04:24:10PM +0200, Arnd Bergmann wrote:
>> > > On Tuesday, July 12, 2016 10:18:11 AM CEST Vivek Goyal wrote:
>> >
>> > /proc/devicetree
On Wed, Jul 13, 2016 at 05:55:33PM +1000, Stewart Smith wrote:
> Russell King - ARM Linux writes:
> > On Wed, Jul 13, 2016 at 02:59:51PM +1000, Stewart Smith wrote:
> >> Russell King - ARM Linux writes:
> >> > On Tue, Jul 12, 2016 at 10:58:05PM +0200, Petr Tesarik wrote:
> >> >> I'm not an expert
[snip]
> Now, going back to the more fundamental issue raised in my first reply,
> about the kernel command line.
>
> On x86, I can see that it _is_ possible for userspace to specify a
> command line, and the kernel loading the image provides the command
> line to the to-be-kexeced kernel with ver
Hi,
The fifth version of this patchset was merged by Andrew Morton
few days ago. It was rebased on v4.7-rc5 so it missed some ongoing
changes.
This is just rebase on next-20160713.
For easier testing the patchset is available here:
repo: https://github.com/krzk/linux
branch: for-next/dma
Split out subsystem specific changes for easier reviews. This will be
squashed with main commit.
Signed-off-by: Krzysztof Kozlowski
---
arch/powerpc/include/asm/dma-mapping.h| 7 +++
arch/powerpc/include/asm/iommu.h | 10 +-
arch/powerpc/kernel/dma-iommu.c | 1
After switching DMA attributes to unsigned long it is easier to just
compare the bits.
Signed-off-by: Krzysztof Kozlowski
[for avr32]
Acked-by: Hans-Christian Noren Egtvedt
[for arc]
Acked-by: Vineet Gupta
[for arm64 and dma-iommu]
Acked-by: Robin Murphy
---
Documentation/DMA-API.txt
The next commit will introduce a member to the kvmppc_vcore struct which
references MAX_SMT_THREADS which is defined in kvm_book3s_asm.h, however
this file isn't included in kvm_host.h directly. Thus compiling for
certain platforms such as pmac32_defconfig and ppc64e_defconfig with KVM
fails due to
The struct kvmppc_vcore is a structure used to store various information
about a virtual core for a kvm guest. The runnable_threads element of the
struct provides a list of all of the currently runnable vcpus on the core
(those in the KVMPPC_VCPU_RUNNABLE state). The previous implementation of
this
This patch introduces new halt polling functionality into the kvm_hv kernel
module. When a vcore is idle it will poll for some period of time before
scheduling itself out.
When all of the runnable vcpus on a vcore have ceded (and thus the vcore is
idle) we schedule ourselves out to allow something
vms and vcpus have statistics associated with them which can be viewed
within the debugfs. Currently it is assumed within the vcpu_stat_get() and
vm_stat_get() functions that all of these statistics are represented as
u32s, however the next patch adds some u64 statistics.
Thus modify these two fun
vcpu stats are used to collect information about a vcpu which can be viewed
in the debugfs. For example halt_attempted_poll and halt_successful_poll
are used to keep track of the number of times the vcpu attempts to and
successfully polls. These stats are currently not used on powerpc.
Implement i
On Wed, 13 Jul 2016 09:26:39 +0100
Russell King - ARM Linux wrote:
> On Wed, Jul 13, 2016 at 05:55:33PM +1000, Stewart Smith wrote:
> > Russell King - ARM Linux writes:
> > > On Wed, Jul 13, 2016 at 02:59:51PM +1000, Stewart Smith wrote:
> > >> Russell King - ARM Linux writes:
> > >> > On Tue,
On 07/13/2016 10:53 AM, Suraj Jitindar Singh wrote:
> vms and vcpus have statistics associated with them which can be viewed
> within the debugfs. Currently it is assumed within the vcpu_stat_get() and
> vm_stat_get() functions that all of these statistics are represented as
> u32s, however the nex
On Wednesday 13 July 2016 01:09 PM, Michael Ellerman wrote:
Arnaldo Carvalho de Melo writes:
Em Tue, Jul 12, 2016 at 07:51:46AM +0530, Ravi Bangoria escreveu:
Hi Arnaldo,
On Friday 08 July 2016 02:01 PM, Michael Ellerman wrote:
Ravi Bangoria writes:
On Wednesday 06 July 2016 03:38 PM,
On Wed, Jul 13, 2016 at 10:36:14AM +0800, Dave Young wrote:
> But consider we can kexec to a different kernel and a different initrd so
> there
> will be use cases to pass a total different dtb as well.
It depends on what you mean by "a different kernel", and what this
implies for the DTB.
I exp
Hi,
This series include cleanup and fixes for radix MMU mode. I also added a
patch that provides a kernel command line option to disable radix.
Aneesh Kumar K.V (11):
powerpc/mm/radix: Update LPCR HR bit as per ISA
powerpc/mm: use _raw variant of page table accessors
powerpc/mm: Compile out
From: Balbir Singh
The .longs with the shifts are harder to read, use more
meaningful names for the opcodes. PPC_TLBIE_5 is introduced
for the 5 opcode variation of the instruction due to an existing
op-code for the 2 opcode variant
Signed-off-by: Balbir Singh
Signed-off-by: Aneesh Kumar K.V
-
PowerISA 3.0 requires the MMU mode (radix vs. hash) of the hypervisor
to be mirrored in the LPCR register, in addition to the partition table.
This is done to avoid fetching from the table when deciding, among other
things, how to perform transitions to HV mode on some interrupts.
So let's set it u
This switch few of the page table accessor to use the __raw variant
and does the cpu to big endian conversion of constants. This helps in
generating better code.
For ex: a pgd_none(pgd) check with and without fix is listed below
Without fix:
2240:20 00 61 eb ld r2
Currently we depend on mmu_has_feature to evalute to zero based on
MMU_FTRS_POSSIBLE mask. In a later patch, we want to update
radix_enabled() to runtime update the conditional operation to a jump
instruction. This implies we cannot depend on MMU_FTRS_POSSIBLE mask.
Instead define radix_enabled to
As per ISA, we need to do this only for architecture version 2.02 and
earlier. This continued to work even for 2.07. But let's not do this for
anything after 2.02. ISA 3.0 requires these top bits to be not cleared.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/mmu.h | 9 +++-
This helps in easily identifying the MMU mode with which the kernel
is operating.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/mm/hash_utils_64.c | 3 ++-
arch/powerpc/mm/pgtable-radix.c | 3 ++-
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/mm/hash_utils_64.c b
ISA 3.0 document hash table size in bytes = 2^(HTABSIZE + 18)
No functionality change by this patch.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/mm/hash_utils_64.c | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm
Update the PID switch as per ISA doc. slbia is needed in radix to
invalidate any implementation specific lookaside information.
We use the .long format due to build errors with the below compiler
version.
gcc (Ubuntu 5.3.1-14ubuntu2.1) 5.3.1 20160413
GNU assembler (GNU Binutils for Ubuntu) 2.26
C
This makes it easy to verify we are not overloading the bits.
No functionality change by this patch.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/reg.h | 56 +-
1 file changed, 28 insertions(+), 28 deletions(-)
diff --git a/arch/powerpc/in
We add a tlb flush variant, to flush LPID mappings.
Signed-off-by: Aneesh Kumar K.V
---
.../powerpc/include/asm/book3s/64/tlbflush-radix.h | 4 +-
arch/powerpc/mm/tlb-radix.c| 52 ++
2 files changed, 55 insertions(+), 1 deletion(-)
diff --git a/arch/
This patch adds the kernel command line disable_radix which disable
the radix MMU mode even if firmware indicates radix support via
ibm,pa-features device tree node.
This helps in testing different MMU mode easily.
Signed-off-by: Aneesh Kumar K.V
---
Documentation/kernel-parameters.txt | 3 +++
This update the machine dep callback such that we can use the same
callback to register process table. The interface is updated such that
we can easily call H_REGISTER_PROC_TBL hcall. The HCALL itself is
introduced in a later patch.
No functionality change introduced by this patch.
Signed-off-by:
Hi,
This patch series add changes to support tracking page size during tlb flush
and use the same in ppc64 so that we can do a tlbie with va range. First
three patches are already in -mm tree.
Aneesh Kumar K.V (13):
mm/hugetlb: Simplify hugetlb unmap
mm: Change the interface for __tlb_remove_
For hugetlb like THP (and unlike regular page), we do tlb flush after
dropping ptl. Because of the above, we don't need to track force_flush
like we do now. Instead we can simply call tlb_remove_page() which
will do the flush if needed.
No functionality change in this patch.
Signed-off-by: Aneesh
This update the generic and arch specific implementation to return true
if we need to do a tlb flush. That means if a __tlb_remove_page indicate
a flush is needed, the page we try to remove need to be tracked and
added again after the flush. We need to track it because we have already
update the pt
This allows arch which need to do special handing with respect to
different page size when flushing tlb to implement the same in mmu gather
Signed-off-by: Aneesh Kumar K.V
---
NOTE: This patch is already applied to -mm tree
arch/arm/include/asm/tlb.h | 12
arch/ia64/include/asm/t
Now that we track page size in mmu_gather, we can use address based
tlbie format when doing a tlb_flush(). We don't do this if we are
invalidating the full address space.
Signed-off-by: Aneesh Kumar K.V
---
.../powerpc/include/asm/book3s/64/tlbflush-radix.h | 2 +
arch/powerpc/mm/tlb-radix.c
MMU feature bits are defined such that we use the lower half to
present MMU family features. Remove the strict split of half and
also move Radix to a mmu family feature. Radix introduce a new MMU
model and strictly speaking it is a new MMU family. This also free
up bits which can be used for indivi
Replace opencoding of the same at multiple places with the helper.
No functional change with this patch.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/mmu-hash.h | 9 +
arch/powerpc/include/asm/kvm_book3s_64.h | 3 +--
arch/powerpc/mm/hash_native_64.c
Use flush_hugetlb_page instead of flush_tlb_page when we clear flush the
pte.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/hugetlb.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/include/asm/hugetlb.h
b/arch/powerpc/include/asm/hugetlb.h
index
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/tlb.h | 13 +
arch/powerpc/mm/tlb-radix.c| 6 --
arch/powerpc/mm/tlb_nohash.c | 6 --
3 files changed, 13 insertions(+), 12 deletions(-)
diff --git a/arch/powerpc/include/asm/tlb.h b/arch/powerpc/include/asm
Instead of flushing the entire mm, implement a flush_pmd_tlb_range
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/tlbflush-radix.h | 2 ++
arch/powerpc/include/asm/book3s/64/tlbflush.h | 9 +
arch/powerpc/mm/pgtable-book3s64.c | 4 ++--
arch
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/tlbflush-radix.h | 10 +-
arch/powerpc/mm/hugetlbpage-radix.c | 4 ++--
arch/powerpc/mm/tlb-radix.c | 16
3 files changed, 15 insertions(+), 15 deletions(-)
di
Use the helper instead of open coding the same at multiple place
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/hugetlb-radix.h | 15 +++
.../powerpc/include/asm/book3s/64/tlbflush-radix.h | 4 +--
arch/powerpc/mm/hugetlbpage-radix.c| 29 ++---
Some archs like ppc64 need to do special things when flushing tlb for
hugepage. Add a new helper to flush hugetlb tlb range. This helps us to
avoid flushing the entire tlb mapping for the pid.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/tlbflush-radix.h | 2 ++
arch/p
This should be same as flush_tlb_page except for hash32. For hash32
I guess the existing code is wrong, because we don't seem to be
flushing tlb for Hash != 0 case at all. Fix this by switching to
calling flush_tlb_page() which does the right thing by flushing
tlb for both hash and nohash case with
Hi,
I have converted the usage of cpu/mmu_has_feature in __init functions
to use the non jump label variant. Even though some of them happen
after featurefix, I guess it is better to have a simpler rule such
that we use __cpu/mmu_has_feature in __init functions and the jump
label variant otherwise
In later patches, we will be switching cpu and mmu feature check to
use static keys. This would require us to have a variant of feature
check that can be used in early boot before jump label is initialized.
This patch adds the same. We also add a variant for radix_enabled()
check
We also update th
This switch most of the early feature check to use the non static key
variant of the function. In later patches we will be switching
cpu_has_feature and mmu_has_feature to use static keys and we can use
them only after static key/jump label is initialized. Any check for
feature before jump label in
We want to use the static key based feature check in set_pte_at. Since
we call radix__map_kernel_page early in boot before jump label is
initialized we can't call set_pte_at there. Add radix__set_pte for the
same.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/mm/pgtable-radix.c | 23 +
From: Kevin Hao
For some archs (such as powerpc) would want to invoke jump_label_init()
in a much earlier stage. So check static_key_initialized in order to
make sure this function run only once.
Signed-off-by: Kevin Hao
Signed-off-by: Aneesh Kumar K.V
---
Ingo did ack this patch in email
htt
Call jump_label_init early so that can use static keys for cpu and
mmu feature check. We should have finalzed all the cpu/mmu features when
we call setup_system and we also did feature fixup for ASM based code.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/kernel/setup_32.c | 6 ++
arch/p
From: Kevin Hao
This function is only used by get_vtb(). They are almost the same
except the reading from the real register. Move the mfspr() to
get_vtb() and kill the function mfvtb(). With this, we can eliminate
the use of cpu_has_feature() in very core header file like reg.h.
This is a prepara
From: Kevin Hao
We plan to use jump label for cpu_has_feature. In order to implement
this we need to include the linux/jump_label.h in asm/cputable.h.
But it seems that asm/cputable.h is so basic header file for ppc that
it is almost included by all the other header files. The including of
the li
From: Kevin Hao
The cpu features are fixed once the probe of cpu features are done.
And the function cpu_has_feature() does be used in some hot path.
The checking of the cpu features for each time of invoking of
cpu_has_feature() seems suboptimal. This tries to reduce this
overhead of this check
From: Kevin Hao
The mmu features are fixed once the probe of mmu features are done.
And the function mmu_has_feature() does be used in some hot path.
The checking of the mmu features for each time of invoking of
mmu_has_feature() seems suboptimal. This tries to reduce this
overhead of this check
This enable us to catch the wrong usage of cpu_has_feature and
mmu_has_feature in the code. We need to use the feature bit based
check in show_regs because that is used in the reporting code.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/Kconfig.debug | 11 +++
arch/powerp
Hi,
This series add support for ISA 3.0 memory segment table.
Aneesh Kumar K.V (2):
powerpc/mm: Switch user slb fault handling to translation enabled
powerpc/mm: Support segment table for Power9
Documentation/kernel-parameters.txt | 3 +
arch/powerpc/include/asm/book3s/64/hash.h
We also handle fault with proper stack initialized. This enable us to
callout to C in fault handling routines. We don't do this for kernel
mapping, because of the possibility of taking recursive fault if kernel
stack in not yet mapped by an slb entry.
This enable us to handle Power9 slb fault bett
PowerISA 3.0 adds an in memory table for storing segment translation
information. In this mode, which is enabled by setting both HOST RADIX
and GUEST RADIX bits in partition table to 0 and enabling UPRT to
1, we have a per process segment table. The segment table details
are stored in the process t
On Wed, Jul 13, 2016 at 10:01:33AM +0200, Arnd Bergmann wrote:
> On Wednesday, July 13, 2016 10:36:14 AM CEST Dave Young wrote:
> > On 07/12/16 at 03:50pm, Mark Rutland wrote:
> > > On Tue, Jul 12, 2016 at 04:24:10PM +0200, Arnd Bergmann wrote:
> > > > On Tuesday, July 12, 2016 10:18:11 AM CEST Viv
Arnaldo, Michael,
I've tested this patchset on ppc64 BE and LE both. Please review this.
-Ravi
On Friday 08 July 2016 10:10 AM, Ravi Bangoria wrote:
Perf can currently only support code navigation (branches and calls) in
annotate when run on the same architecture where perf.data was recorded.
The udc->eps[] array has USB_MAX_ENDPOINTS elements so > should be >=.
Fixes: 3948f0e0c999 ('usb: add Freescale QE/CPM USB peripheral controller
driver')
Signed-off-by: Dan Carpenter
diff --git a/drivers/usb/gadget/udc/fsl_qe_udc.c
b/drivers/usb/gadget/udc/fsl_qe_udc.c
index 93d28cb..cf8819a 1
Hello Benjamin Herrenschmidt,
The patch ac171c46667c: "[PATCH] powerpc: Thermal control for dual
core G5s" from Feb 8, 2006, leads to the following static checker
warning:
drivers/macintosh/windfarm_smu_controls.c:83 smu_set_fan()
warn: buffer overflow 'buffer' 16 <= 16
drivers/m
Hello Christophe Lombard,
The patch 4752876c7170: "cxl: sysfs support for guests" from Mar 4,
2016, leads to the following static checker warning:
drivers/misc/cxl/sysfs.c:681 cxl_sysfs_afu_add()
warn: if statement not indented
drivers/misc/cxl/sysfs.c
672 err1:
673
On Wed, 2016-07-13 at 15:10 +0530, Aneesh Kumar K.V wrote:
> Hi,
>
> This series add support for ISA 3.0 memory segment table.
>
> Aneesh Kumar K.V (2):
> powerpc/mm: Switch user slb fault handling to translation enabled
> powerpc/mm: Support segment table for Power9
The segment table will o
On Wed, 2016-07-13 at 15:08 +0530, Aneesh Kumar K.V wrote:
> This switch most of the early feature check to use the non static key
> variant of the function. In later patches we will be switching
> cpu_has_feature and mmu_has_feature to use static keys and we can use
> them only after static key/ju
On Wed, Jul 13, 2016 at 09:26:39AM +0100, Russell King - ARM Linux wrote:
> On Wed, Jul 13, 2016 at 05:55:33PM +1000, Stewart Smith wrote:
> > Russell King - ARM Linux writes:
> > > On Wed, Jul 13, 2016 at 02:59:51PM +1000, Stewart Smith wrote:
> > >> Russell King - ARM Linux writes:
> > >> > On
On Wednesday, July 13, 2016 10:41:28 AM CEST Mark Rutland wrote:
> On Wed, Jul 13, 2016 at 10:01:33AM +0200, Arnd Bergmann wrote:
> > On Wednesday, July 13, 2016 10:36:14 AM CEST Dave Young wrote:
> > > On 07/12/16 at 03:50pm, Mark Rutland wrote:
> > > > On Tue, Jul 12, 2016 at 04:24:10PM +0200, Ar
On Wed, Jul 13, 2016 at 09:41:39AM +1000, Stewart Smith wrote:
> Petr Tesarik writes:
> > On Tue, 12 Jul 2016 13:25:11 -0300
> > Thiago Jung Bauermann wrote:
> >
> >> Hi Eric,
> >>
> >> I'm trying to understand your concerns leading to your nack. I hope you
> >> don't mind expanding your though
On Wed, Jul 13, 2016 at 09:45:22AM +1000, Stewart Smith wrote:
> Vivek Goyal writes:
> > On Tue, Jul 12, 2016 at 10:58:09AM -0300, Thiago Jung Bauermann wrote:
> >> Hello Eric,
> >>
> >> Am Dienstag, 12 Juli 2016, 08:25:48 schrieb Eric W. Biederman:
> >> > AKASHI Takahiro writes:
> >> > > Device
Wed, Jul 13, 2016 at 01:05:03PM +1000, Stewart Smith wrote:
> Stephen Rothwell writes:
> > On Mon, 11 Jul 2016 16:07:39 -0300 Paulo Flabiano Smorigo
> > wrote:
> >>
> >> diff --git a/drivers/crypto/vmx/aesp8-ppc.pl
> >> b/drivers/crypto/vmx/aesp8-ppc.pl
> >> index 2280539..813ffcc 100644
> >> -
On 07/12/2016 08:07 PM, Mauricio Faria de Oliveira wrote:
Can you clarify which are the devices that should be tracked w/ krefs to
the PHB?
Last night I had forgotten about the fundamental point of krefs - track
references to pointers - and this answers the question.
I'm looking at the holde
Benjamin Herrenschmidt writes:
> On Wed, 2016-07-13 at 15:08 +0530, Aneesh Kumar K.V wrote:
>> This switch most of the early feature check to use the non static key
>> variant of the function. In later patches we will be switching
>> cpu_has_feature and mmu_has_feature to use static keys and we c
Benjamin Herrenschmidt writes:
> On Wed, 2016-07-13 at 15:10 +0530, Aneesh Kumar K.V wrote:
>> Hi,
>>
>> This series add support for ISA 3.0 memory segment table.
>>
>> Aneesh Kumar K.V (2):
>> powerpc/mm: Switch user slb fault handling to translation enabled
>> powerpc/mm: Support segment
Benjamin Herrenschmidt writes:
> On Wed, 2016-07-13 at 15:08 +0530, Aneesh Kumar K.V wrote:
>> This switch most of the early feature check to use the non static key
>> variant of the function. In later patches we will be switching
>> cpu_has_feature and mmu_has_feature to use static keys and we c
Hello Markos Chandras,
The patch c6610de353da: "MIPS: net: Add BPF JIT" from Apr 8, 2014,
leads to the following static checker warning:
arch/mips/net/bpf_jit.c:1185 build_body()
warn: potential off by one 'ctx->offsets[]' limit 'prog->len'
arch/mips/net/bpf_jit.c
652 static
On Wed, 2016-07-13 at 19:36 +0530, Aneesh Kumar K.V wrote:
> > I'm not sure about that. This is converting way way way way more
> > functions than is needed. Especially if Michael applies my series
> > there will be very little code run before the patching, really only
> the
> > MMU initialization.
Hi Paulo,
On Wed, 13 Jul 2016 10:34:27 -0300 Paulo Flabiano Smorigo
wrote:
>
> Wed, Jul 13, 2016 at 01:05:03PM +1000, Stewart Smith wrote:
> > Stephen Rothwell writes:
> > > On Mon, 11 Jul 2016 16:07:39 -0300 Paulo Flabiano Smorigo
> > > wrote:
> > >>
> > >> diff --git a/drivers/crypto/vm
Thu, Jul 14, 2016 at 01:11:58AM +1000, Stephen Rothwell wrote:
> Hi Paulo,
>
> On Wed, 13 Jul 2016 10:34:27 -0300 Paulo Flabiano Smorigo
> wrote:
> >
> > Wed, Jul 13, 2016 at 01:05:03PM +1000, Stewart Smith wrote:
> > > Stephen Rothwell writes:
> > > > On Mon, 11 Jul 2016 16:07:39 -0300 Paulo
From: Thomas Gleixner
Install the callbacks via the state machine and let the core invoke
the callbacks on the already online CPUs.
Signed-off-by: Thomas Gleixner
Reviewed-by: Sebastian Andrzej Siewior
Cc: Anshuman Khandual
Cc: Benjamin Herrenschmidt
Cc: Linus Torvalds
Cc: Madhavan Srinivas
From: Sebastian Andrzej Siewior
Install the callbacks via the state machine and let the core invoke
the callbacks on the already online CPUs.
Signed-off-by: Sebastian Andrzej Siewior
Cc: Andrew Morton
Cc: Benjamin Herrenschmidt
Cc: Bharata B Rao
Cc: Christophe Jaillet
Cc: Linus Torvalds
Cc
On Tue, Jul 12, 2016 at 11:07 PM, Suraj Jitindar Singh
wrote:
> On 12/07/16 16:17, Suraj Jitindar Singh wrote:
>> On 12/07/16 02:49, David Matlack wrote:
[snip]
>>> It's possible to poll and wait in one halt, conflating this stat with
>>> polling time. Is it useful to split out a third stat,
>>> h
Apologies for the slow response. I'm attending LinuxCon this week.
On Wed, Jul 13, 2016 at 10:34:47AM +0100, Mark Rutland wrote:
> On Wed, Jul 13, 2016 at 10:36:14AM +0800, Dave Young wrote:
> > But consider we can kexec to a different kernel and a different initrd so
> > there
> > will be use ca
On Wed, Jul 13, 2016 at 09:03:38AM -0400, Vivek Goyal wrote:
> On Wed, Jul 13, 2016 at 09:26:39AM +0100, Russell King - ARM Linux wrote:
> > Indeed - maybe Eric knows better, but I can't see any situation where
> > the dtb we load via kexec should ever affect "the bootloader", unless
> > the "kerne
On Thu, Jul 14, 2016 at 02:38:06AM +0900, AKASHI Takahiro wrote:
> Apologies for the slow response. I'm attending LinuxCon this week.
>
> On Wed, Jul 13, 2016 at 10:34:47AM +0100, Mark Rutland wrote:
> > On Wed, Jul 13, 2016 at 10:36:14AM +0800, Dave Young wrote:
> > > But consider we can kexec to
On 07/11/2016 09:31 PM, Paolo Bonzini wrote:
>
>
> On 11/07/2016 19:30, David Matlack wrote:
>> On Mon, Jul 11, 2016 at 10:05 AM, Paolo Bonzini wrote:
>>>
>>>
>>> On 11/07/2016 18:51, David Matlack wrote:
>> vcpus have statistics associated with them which can be viewed within the
>> deb
On Wed, Jul 13, 2016 at 06:40:10PM +0100, Russell King - ARM Linux wrote:
> On Wed, Jul 13, 2016 at 09:03:38AM -0400, Vivek Goyal wrote:
> > On Wed, Jul 13, 2016 at 09:26:39AM +0100, Russell King - ARM Linux wrote:
> > > Indeed - maybe Eric knows better, but I can't see any situation where
> > > th
Am Mittwoch, 13 Juli 2016, 15:13:42 schrieb Arnd Bergmann:
> On Wednesday, July 13, 2016 10:41:28 AM CEST Mark Rutland wrote:
> > On Wed, Jul 13, 2016 at 10:01:33AM +0200, Arnd Bergmann wrote:
> > > - kboot/petitboot with all of the user space being part of the trusted
> > > boot> >
> > > chain:
On Wednesday, July 13, 2016 6:58:32 PM CEST Mark Rutland wrote:
>
> > we may want to remove unnecessary devices and even add a dedicated
> > storage device for storing a core dump image.
>
> I suspect that bringing up a minimal number of devices is better
> controlled by a cmdline option. In
On Wednesday, July 13, 2016 3:45:41 PM CEST Thiago Jung Bauermann wrote:
> Am Mittwoch, 13 Juli 2016, 15:13:42 schrieb Arnd Bergmann:
> > On Wednesday, July 13, 2016 10:41:28 AM CEST Mark Rutland wrote:
> > > On Wed, Jul 13, 2016 at 10:01:33AM +0200, Arnd Bergmann wrote:
> > > > - kboot/petitboot w
Excerpts from andrew.donnellan's message of 2016-07-12 20:39:13 +1000:
> Some comments below - with those addressed:
>
> Reviewed-by: Andrew Donnellan
Thanks for the review :)
> > V1->V2:
> > - Add an explanation of the peer model to the commit message,
> > and a comment above the pnv
On 06/30/2016 04:44 PM, Michael Bringmann wrote:
> Several properties in the DRC device tree format are replaced by
> more compact representations to allow, for example, for the encoding
> of vast amounts of memory, and or reduced duplication of information
> in related data structures.
>
> "ibm,d
Excerpts from andrew.donnellan's message of 2016-07-13 15:52:45 +1000:
> > +bool _cxl_pci_associate_default_context(struct pci_dev *dev, struct
> > cxl_afu *afu)
>
> If we're sharing these functions between the vPHB and peer models, do we
> have a better place than vphb.c for them?
Sure, I migh
This series adds support for the Mellanox CX4 network adapter operating in cxl
mode to the cxl driver and the PowerNV PHB code. The Mellanox developers will
submit a separate patch series that makes use of this in the mlx5 driver.
The CX4 card can operate in either pci mode, or cxl mode. In cxl mo
From: Ian Munsie
The support for using the Mellanox CX4 in cxl mode will require
additions to the PHB code. In preparation for this, move the existing
cxl code out of pci-ioda.c into a separate pci-cxl.c file to keep things
more organised.
Signed-off-by: Ian Munsie
Reviewed-by: Andrew Donnellan
From: Ian Munsie
This extends the check that the adapter is in a CAPI capable slot so
that it may be called by external users in the kernel API. This will be
used by the upcoming Mellanox CX4 support, which needs to know ahead of
time if the card can be switched to cxl mode so that it can leave i
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