On Mon, 23 May 2016, Russell Currey wrote:
> On Sat, 2016-05-21 at 14:03 +0200, Andrea Gelmini wrote:
> > Signed-off-by: Andrea Gelmini
> > ---
>
> This entire comment needs to be rewritten as it's incredibly confusing, but
> alas
>
> Acked-by: Russell Currey
>
> > arch/powerpc/include/asm/eeh
On Fri, 20 May 2016 04:41:34 +1000
Anton Blanchard via Linuxppc-dev wrote:
> The comment explaining why we modify VRSAVE is misleading, glibc
> does rely on the behaviour. Update the comment.
>
> Signed-off-by: Anton Blanchard
> ---
>
> diff --git a/arch/powerpc/kernel/vector.S b/arch/powerpc/
Hi All,
You removed PAGE_GUARDED in the commit
https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=c04a5880299eab3da8c10547db96ea9cdffd44a6
We use
range.size, _PAGE_NO_CACHE|_PAGE_GUARDED);
This doesn't work anymore. What can we use instead?
Thanks in advance,
Christ
On Mon, 2016-05-23 at 06:38 +0200, Christian Zigotzky wrote:
> Hi All,
>
> You removed PAGE_GUARDED in the commit
>
> https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commi
> t/?id=c04a5880299eab3da8c10547db96ea9cdffd44a6
>
> We use
>
> range.size, _PAGE_NO_CACHE|_PAGE_GUARDED)
A strange behaviour is observed when comparing PCI hotplug in QEMU, between
x86 and pseries. If you consider the following steps:
- start a VM
- add a PCI device via the QEMU monitor before the rtasd has started (for
example starting the VM in paused state, or hotplug during FW or boot
loader)
sub_reloc_offset() has not been used since
commit 917f0af9e5a9 ("powerpc: Remove arch/ppc and include/asm-ppc")
which removed include/asm-ppc/prom.h
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/misc_32.S | 14 --
1 file changed, 14 deletions(-)
diff --git a/arch/powerpc/k
current_stack_pointeur() is a single instruction function. it
It is not worth breaking the execution flow with a bl/blr for a
single instruction
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/reg.h | 7 ++-
arch/powerpc/kernel/misc.S | 4
arch/powerpc/kernel/ppc_ksym
lmw/stmw have a 1 cycle (2 cycles for lmw on some ppc) in addition
and implies serialising, however it reduces the amount of instructions
hence the amount of instruction fetch compared to the equivalent
operation with several lzw/stw. It means less pressure on cache and
less fetching delays on slow
On Sun, May 22, 2016 at 01:42:52PM -0700, Steve Muckle wrote:
> On Sun, May 22, 2016 at 12:39:12PM +0200, Peter Zijlstra wrote:
> > On Fri, May 20, 2016 at 05:53:41PM +0530, Shilpasri G Bhat wrote:
> > >
> > > Below are the comparisons by disabling watchdog.
> > > Both schedutil and ondemand have
On Sun, May 22, 2016 at 01:42:52PM -0700, Steve Muckle wrote:
> > So does it actually matter what the frequency is when you idle? Isn't
> > the whole thing clock gated anyway?
> >
> > Because this seems to generate contradictory requirements, on the one
> > hand we want to stay idle as long as po
On Mon, May 23, 2016 at 10:00:04AM +0100, Lorenzo Pieralisi wrote:
> It is also related to static leakage power that depends on the operating
> voltage (ie higher operating frequencies require higher voltage) so in a
> way scaling frequency before going idle may not be effective if voltage
> does n
From: Jiri Kosina
> Sent: 18 May 2016 21:23
> On Wed, 18 May 2016, Josh Poimboeuf wrote:
>
> > Yeah, I think this situation -- a task sleeping on an affected function
> > in uninterruptible state for a long period of time -- would be
> > exceedingly rare and not something we need to worry about fo
This adds an afu_driver_ops structure with deliver_event() and
event_delivered() callbacks. An AFU driver such as cxlflash can fill
this out and associate it with a context to enable passing custom
AFU specific events to userspace.
This also adds a new kernel API function cxl_context_pending_event
From: Michael Neuling
This provides AFU drivers a means to associate private data with a cxl
context. This is particularly intended for make the new callbacks for
driver specific events easier for AFU drivers to use, as they can easily
get back to any private data structures they may use.
Signed
From: Michael Neuling
This provides AFU drivers a means to associate private data with a cxl
context. This is particularly intended for make the new callbacks for
driver specific events easier for AFU drivers to use, as they can easily
get back to any private data structures they may use.
Signed
POWER ISA v3 defines a new idle processor core mechanism. In summary,
a) new instruction named stop is added. This instruction replaces
instructions like nap, sleep, rvwinkle.
b) new per thread SPR named PSSCR is added which controls the behavior
of stop instruction.
In the current code, when the thread wakes up in reset vector, some
of the state restore code and check for whether a thread needs to
branch to kvm is duplicated. Reorder the code such that this
duplication is avoided.
At a higher level this is what the change looks like-
Before this patch -
powe
idle_power7.S handles idle entry/exit for POWER7, POWER8 and in next
patch for POWER9. Rename the file to a non-hardware specific
name.
Signed-off-by: Shreyas B. Prabhu
---
Changes in v3:
==
- Instead of moving few common functions from idle_power7.S to
idle_power_common.S, renami
Functions like power7_wakeup_loss, power7_wakeup_noloss,
power7_wakeup_tb_loss are used by POWER7 and POWER8 hardware. They can
also be used by POWER9. Hence rename these functions hardware agnostic
names.
Suggested-by: Gautham R. Shenoy
Signed-off-by: Shreyas B. Prabhu
---
New in v3
arch/powe
power7_powersave_common does common steps needed before entering idle
state and eventually changes MSR to MSR_IDLE and does rfid to
power7_enter_nap_mode.
Move the updation of HSTATE_HWTHREAD_STATE to power7_powersave_common
from power7_enter_nap_mode and make it more generic by passing the rfid
a
Create a function for saving SPRs before entering deep idle states.
This function can be reused for POWER9 deep idle states.
Signed-off-by: Shreyas B. Prabhu
---
New in v3
arch/powerpc/kernel/idle_power_common.S | 54 +++--
1 file changed, 32 insertions(+), 22 deleti
pnv_init_idle_states discovers supported idle states from the
device tree and does the required initialization. Set power_save
function pointer only after this initialization is done
Reviewed-by: Gautham R. Shenoy
Signed-off-by: Shreyas B. Prabhu
---
arch/powerpc/platforms/powernv/idle.c | 3 +
POWER ISA v3 defines a new idle processor core mechanism. In summary,
a) new instruction named stop is added. This instruction replaces
instructions like nap, sleep, rvwinkle.
b) new per thread SPR named PSSCR is added which controls the behavior
of stop instruction.
PSSCR has fo
POWER ISA v3 defines a new idle processor core mechanism. In summary,
a) new instruction named stop is added.
b) new per thread SPR named PSSCR is added which controls the behavior
of stop instruction.
Supported idle states and value to be written to PSSCR register to enter
any idle stat
If hardware supports stop state, use the deepest stop state when
the cpu is offlined.
Reviewed-by: Gautham R. Shenoy
Signed-off-by: Shreyas B. Prabhu
---
arch/powerpc/platforms/powernv/idle.c| 15 +--
arch/powerpc/platforms/powernv/powernv.h | 1 +
arch/powerpc/platforms/powern
From: Ian Munsie
In the kernel API, it is possible to attempt to allocate AFU interrupts
after already starting a context. Since the process element structure
used by the hardware is only filled out at the time the context is
started, it will not be updated with the interrupt numbers that have
ju
From: Frederic Barrat
The XSL (Translation Service Layer) is a stripped down version of the
PSL (Power Service Layer) used in some cards such as the Mellanox CX4.
Like the PSL, it implements the CAIA architecture, but has a number of
differences, mostly in it's implementation dependent registers
On 23.05.2016 10:28, Greg Kurz wrote:
> A strange behaviour is observed when comparing PCI hotplug in QEMU, between
> x86 and pseries. If you consider the following steps:
> - start a VM
> - add a PCI device via the QEMU monitor before the rtasd has started (for
> example starting the VM in pause
On Mon, 23 May 2016 20:23:19 +0200
Thomas Huth wrote:
> On 23.05.2016 10:28, Greg Kurz wrote:
> > A strange behaviour is observed when comparing PCI hotplug in QEMU, between
> > x86 and pseries. If you consider the following steps:
> > - start a VM
> > - add a PCI device via the QEMU monitor befo
On Mon, 23 May 2016, David Laight wrote:
> Related, please can we have a flag for the sleep and/or process so that
> an uninterruptible sleep doesn't trigger the 'hung task' detector
TASK_KILLABLE
> and also stops the process counting towards the 'load average'.
TASK_NOLOAD
--
Jiri Kosina
SUS
On Mon, May 23, 2016 at 10:46:36AM +0200, Christophe Leroy wrote:
> lmw/stmw have a 1 cycle (2 cycles for lmw on some ppc) in addition
> and implies serialising, however it reduces the amount of instructions
> hence the amount of instruction fetch compared to the equivalent
> operation with several
On Mon, May 23, 2016 at 10:46:02AM +0200, Christophe Leroy wrote:
> +static inline unsigned long current_stack_pointer(void)
> +{
> + register unsigned long *ptr asm("r1");
> +
> + return *ptr;
> +}
Register asm is only guaranteed to work as input to inline asm. NAK.
Segher
On Thu, May 19, 2016 at 01:24:12PM -0700, Josh Triplett wrote:
> On Thu, May 19, 2016 at 12:38:47PM -0700, Paul E. McKenney wrote:
> > On Thu, May 19, 2016 at 09:23:39AM -0700, Paul E. McKenney wrote:
> > > On Thu, May 19, 2016 at 08:40:42AM -0700, Josh Triplett wrote:
> > > > On Thu, May 19, 2016
On Thu, May 19, 2016 at 4:15 PM, Josh Poimboeuf wrote:
> On Mon, May 02, 2016 at 08:52:41AM -0700, Andy Lutomirski wrote:
>> On Mon, May 2, 2016 at 6:52 AM, Josh Poimboeuf wrote:
>> > On Fri, Apr 29, 2016 at 05:08:50PM -0700, Andy Lutomirski wrote:
>> >> On Apr 29, 2016 3:41 PM, "Josh Poimboeuf"
On Fri, 20 May 2016, Andy Lutomirski wrote:
> I think it would be negligible, at least for interrupts, since
> interrupts are already extremely expensive. But I don't love adding
> assembly code that makes them even slower. The real thing I dislike
> about this approach is that it's not a normal
On Mon, 2016-05-23 at 03:12 -0400, Robert P. J. Day wrote:
> On Mon, 23 May 2016, Russell Currey wrote:
>
> > On Sat, 2016-05-21 at 14:03 +0200, Andrea Gelmini wrote:
> > > Signed-off-by: Andrea Gelmini
> > > ---
> >
> > This entire comment needs to be rewritten as it's incredibly confusing, but
On Mon, May 23, 2016 at 4:02 PM, Jiri Kosina wrote:
> On Fri, 20 May 2016, Andy Lutomirski wrote:
>
>> I think it would be negligible, at least for interrupts, since
>> interrupts are already extremely expensive. But I don't love adding
>> assembly code that makes them even slower. The real thin
On Mon, May 23, 2016 at 02:34:56PM -0700, Andy Lutomirski wrote:
> On Thu, May 19, 2016 at 4:15 PM, Josh Poimboeuf wrote:
> > On Mon, May 02, 2016 at 08:52:41AM -0700, Andy Lutomirski wrote:
> >> On Mon, May 2, 2016 at 6:52 AM, Josh Poimboeuf wrote:
> >> > On Fri, Apr 29, 2016 at 05:08:50PM -0700
On Tue, 2016-05-24 at 10:04 +1000, Russell Currey wrote:
> On Mon, 2016-05-23 at 03:12 -0400, Robert P. J. Day wrote:
> > On Mon, 23 May 2016, Russell Currey wrote:
> > > On Sat, 2016-05-21 at 14:03 +0200, Andrea Gelmini wrote:
> > > > Signed-off-by: Andrea Gelmini
> > > > ---
> > >
> > > This en
On May 23, 2016 7:28 PM, "Josh Poimboeuf" wrote:
> > Maybe I'm coming around to liking this idea.
>
> Ok, good :-)
>
> > In an ideal world (DWARF support, high-quality unwinder, nice pretty
> > printer, etc), unwinding across a kernel exception would look like:
> >
> > - some_func
> > - some_oth
Le 23/05/2016 à 22:22, Segher Boessenkool a écrit :
On Mon, May 23, 2016 at 10:46:02AM +0200, Christophe Leroy wrote:
+static inline unsigned long current_stack_pointer(void)
+{
+ register unsigned long *ptr asm("r1");
+
+ return *ptr;
+}
Register asm is only guaranteed to work as
Hi,
On Friday 20 May 2016 06:07 PM, Masami Hiramatsu wrote:
Hi Anju,
Please see my comments below,
On Thu, 19 May 2016 20:40:39 +0530
Anju T wrote:
ppc_get_optinsn_slot() and ppc_free_optinsn_slot() are
geared towards the allocation and freeing of memory from
the area reserved for detour buf
On Tue, May 24, 2016 at 07:39:59AM +0200, Christophe Leroy wrote:
> >>+static inline unsigned long current_stack_pointer(void)
> >>+{
> >>+ register unsigned long *ptr asm("r1");
> >>+
> >>+ return *ptr;
> >>+}
> >Register asm is only guaranteed to work as input to inline asm. NAK.
> >
> Does
On Mon, May 23, 2016 at 10:46:02AM +0200, Christophe Leroy wrote:
> current_stack_pointeur() is a single instruction function. it
> It is not worth breaking the execution flow with a bl/blr for a
> single instruction
Are you sure that the result is always the same?
Calling an external function p
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