From: Ian Munsie
cxl devices typically access memory using an MMU in much the same way as
the CPU, and each context includes a state register much like the MSR in
the CPU. Like the CPU, the state register includes a bit to enable
relocation, which we currently always enable.
In some cases, it ma
POWER ISA v3 adds large decrementer (LD) mode of operation which increases
the size of the decrementer register from 32 bits to an implementation
defined with of up to 64 bits.
This patch adds support for the LD on processors with the CPU_FTR_ARCH_300
cpu feature flag set. Even for CPUs with this
Power ISAv3 extends the width of the decrementer register from 32 bits.
The enlarged register width is implementation dependent, but reads from
these registers are automatically sign extended to produce a 64 bit output
when operating in large mode. The HDEC always operates in large mode
while the D
On 4 May 2016 at 05:24, Yangbo Lu wrote:
> Add maintainer entry for Freescale SoC driver including
> the QE library and the GUTS driver now. Also add maintainer
> for QE library.
>
> Signed-off-by: Yangbo Lu
So I need an ack from Scott and Qiang for this one, then I intend to
queue up the series
On 05/03/2016 03:41 PM, Gavin Shan wrote:
This changes the data type of PE number from "int" to "unsigned int"
in order to match the fact PE number is never negative:
* The number of PE to which the specified PCI device is attached.
* The PE number map for SRIOV VFs.
* The returned PE n
On Thu 2016-04-28 15:44:48, Josh Poimboeuf wrote:
> Change livepatch to use a basic per-task consistency model. This is the
> foundation which will eventually enable us to patch those ~10% of
> security patches which change function or data semantics. This is the
> biggest remaining piece needed
On Mon, 2016-04-18 at 16:08 -0500, Jack Miller wrote:
> Adds two tests. One is a simple test to ensure that the new registers
> LMRR and LMSER are properly maintained. The other actually uses the
> existing EBB test infrastructure to test that LMRR and LMSER behave as
> documented.
>
> Signed-off-
From: Jack Miller
Previously we just saved the FSCR, but only restored it in some
settings, and never copied it thread to thread. This patch always
restores the FSCR and formalizes new threads inheriting its setting so
that later we can manipulate FSCR bits in start_thread.
Signed-off-by: Jack M
On Wed, 2016-05-04 at 20:43 +1000, Michael Neuling wrote:
> On Mon, 2016-04-18 at 16:08 -0500, Jack Miller wrote:
> > +int ebb_lmr(void)
> > +{
> > + int i;
> > +
> > + SKIP_IF(!ebb_is_supported());
>
> We skip this test currently as EBB is not enabled on POWER9.
>
> On POWER8 we enable EBB
On Wed, 2016-05-04 at 21:31 +1000, Michael Ellerman wrote:
> On Wed, 2016-05-04 at 20:43 +1000, Michael Neuling wrote:
> >
> > On Mon, 2016-04-18 at 16:08 -0500, Jack Miller wrote:
> >
> > >
> > > +int ebb_lmr(void)
> > > +{
> > > + int i;
> > > +
> > > + SKIP_IF(!ebb_is_supported());
> > We ski
On Tue, Apr 26, 2016 at 12:03 PM, Andy Shevchenko
wrote:
> The last approach in the commit 8b3444852a2b ("sata_dwc_460ex: move to generic
> DMA driver") to switch to generic DMA engine API wasn't tested on bare metal.
> Besides that we expecting new board support coming with the same SATA IP but
>
On Thu 2016-04-28 15:44:48, Josh Poimboeuf wrote:
> Change livepatch to use a basic per-task consistency model. This is the
> foundation which will eventually enable us to patch those ~10% of
> security patches which change function or data semantics. This is the
> biggest remaining piece needed
On Tue, May 03, 2016 at 03:41:35PM +1000, Gavin Shan wrote:
>In current implementation, the DMA32 segments required by one specific
>PE isn't calculated with the information hold in the PE independently.
>It conflicts with the PCI hotplug design: PE centralized, meaning the
>PE's DMA32 segments sho
On Tue, May 03, 2016 at 11:22:52PM +1000, Gavin Shan wrote:
>This exports of_detach_node() for PowerPC PowerNV PCI hotplug
>driver. No functional changes introduced.
>
>Signed-off-by: Gavin Shan
Rob, I'm not sure it's late to cache the 4.7 merge window.
Also, I was told this series is needed by n
On Wed, May 04, 2016 at 02:39:40PM +0200, Petr Mladek wrote:
> > +* This barrier also ensures that if another CPU goes through the
> > +* syscall barrier, sees the TIF_PATCH_PENDING writes in
> > +* klp_start_transition(), and calls klp_patch_task(), it also sees the
> > +* above wr
On Wed 2016-05-04 14:39:40, Petr Mladek wrote:
>*
>* Note that the task must never be migrated to the target
>* state when being inside this ftrace handler.
>*/
>
> We might want to move the second paragraph on top of the function.
>
Hi Ian,
diff --git a/drivers/misc/cxl/guest.c b/drivers/misc/cxl/guest.c
index c0cdf3c..04f6dff 100644
--- a/drivers/misc/cxl/guest.c
+++ b/drivers/misc/cxl/guest.c
@@ -552,6 +552,17 @@ static int attach_afu_directed(struct cxl_context *ctx,
u64 wed, u64 amr)
elem->common.sstp0 = cpu
On Thu 2016-04-28 15:44:48, Josh Poimboeuf wrote:
> Change livepatch to use a basic per-task consistency model. This is the
> foundation which will eventually enable us to patch those ~10% of
> security patches which change function or data semantics. This is the
> biggest remaining piece needed
On Wed, 4 May 2016, Petr Mladek wrote:
> > +
> > + if (unlikely(klp_patch_pending(current)))
> > + klp_patch_task(current);
> > }
>
> Some more ideas from the world of crazy races. I was shaking my head
> if this was safe or not.
>
> The problem might be if the ta
From: Andy Lutomirski
> Sent: 02 May 2016 19:13
...
> I hope your plans include rewriting the current stack unwinder
> completely. The thing in print_context_stack is (a)
> hard-to-understand and hard-to-modify crap and (b) is called in a loop
> from another file using totally ridiculous conventio
On 04/18/2016 10:54 PM, Bharata B Rao wrote:
> On Sat, Apr 09, 2016 at 03:44:31PM +0530, Bharata B Rao wrote:
>> On Fri, Apr 08, 2016 at 12:27:44AM -0500, Nathan Fontenot wrote:
>>> On 04/06/2016 04:44 AM, Bharata B Rao wrote:
memory_hotplug_max() uses hot_add_drconf_memory_max() to get maxmim
On Wed, May 04, 2016 at 10:42:23AM +0200, Petr Mladek wrote:
> On Thu 2016-04-28 15:44:48, Josh Poimboeuf wrote:
> > Change livepatch to use a basic per-task consistency model. This is the
> > foundation which will eventually enable us to patch those ~10% of
> > security patches which change funct
Hi Ian,
The principle is fine, but the cxl_start_context2 API bothers me a bit.
Would something similar to this make sense, I think it would keep the
API cleaner:
/* new kernel-only API */
void cxl_set_translation_mode(struct cxl_context *ctx, bool real_mode)
For mlx5, the call sequence woul
On Wed, May 04, 2016 at 03:53:29PM +0200, Peter Zijlstra wrote:
> On Wed, May 04, 2016 at 02:39:40PM +0200, Petr Mladek wrote:
> > > + * This barrier also ensures that if another CPU goes through the
> > > + * syscall barrier, sees the TIF_PATCH_PENDING writes in
> > > + * klp_start_transition()
On Wed, May 04, 2016 at 02:39:40PM +0200, Petr Mladek wrote:
> On Thu 2016-04-28 15:44:48, Josh Poimboeuf wrote:
> > Change livepatch to use a basic per-task consistency model. This is the
> > foundation which will eventually enable us to patch those ~10% of
> > security patches which change funct
On Wed, May 04, 2016 at 04:12:05PM +0200, Petr Mladek wrote:
> On Wed 2016-05-04 14:39:40, Petr Mladek wrote:
> > *
> > * Note that the task must never be migrated to the target
> > * state when being inside this ftrace handler.
> > */
> >
> > We
On Wed, 2016-05-04 at 11:24 +0800, Yangbo Lu wrote:
> Add maintainer entry for Freescale SoC driver including
> the QE library and the GUTS driver now. Also add maintainer
> for QE library.
>
> Signed-off-by: Yangbo Lu
> ---
> Changes for v8:
> - Added this patch
> Changes for v9:
> -
On Wed, May 04, 2016 at 04:48:54PM +0200, Petr Mladek wrote:
> On Thu 2016-04-28 15:44:48, Josh Poimboeuf wrote:
> > Change livepatch to use a basic per-task consistency model. This is the
> > foundation which will eventually enable us to patch those ~10% of
> > security patches which change funct
This will allow device drivers to consistently use io{read,write}XX
also for 64-bit accesses.
Signed-off-by: Horia Geantă
---
arch/powerpc/kernel/iomap.c | 24
1 file changed, 24 insertions(+)
diff --git a/arch/powerpc/kernel/iomap.c b/arch/powerpc/kernel/iomap.c
index
On Tuesday, April 19, 2016 03:27:59 PM Akshay Adiga wrote:
> The frequency transition latency from pmin to pmax is observed to be in few
> millisecond granurality. And it usually happens to take a performance penalty
> during sudden frequency rampup requests.
>
> This patch set solves this problem
Hi Balbir,
On 05/01/2016 09:05 PM, Balbir Singh wrote:
> On 29/04/16 01:18, Christopher Covington wrote:
>> In order to share remap and unmap support for the VDSO with other
>> architectures without duplicating the code, we need a common name and type
>> for the address of the VDSO. An informal su
Acked-by: Matthew R. Ochs
___
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Linuxppc-dev@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/linuxppc-dev
On Thu, 2016-28-04 at 05:34:54 UTC, Suraj Jitindar Singh wrote:
> The validity of the property input argument to of_remove_property() is
> never checked within the function and thus it is possible to pass a null
> value. It happens that this will be picked up in __of_remove_property()
> as no match
On Mon, 2016-02-05 at 10:51:50 UTC, "Aneesh Kumar K.V" wrote:
> Check against a context.id value of zero instead of MMU_NO_CONTEXT
> when doing a slice psize init. Without this patch we end up with
> a slice psize value of zero and we always end up using 4K hpte.
>
> Signed-off-by: Aneesh Kumar K.
On Thu, 2016-28-04 at 05:34:55 UTC, Suraj Jitindar Singh wrote:
> After obtaining a property from of_find_property() and before calling
> of_remove_property() most code checks to ensure that the property
> returned from of_find_property() is not null. The previous patch
> moved this check to the st
On Thu, 2016-28-04 at 05:53:45 UTC, Suraj Jitindar Singh wrote:
> The return value of of_get_property() isn't checked before it is passed
> to the strstr() function, if it happens that the return value is null
> then this will result in a null pointer being dereferenced.
>
> Add a check to see if
On Tue, 2016-03-05 at 06:59:27 UTC, Valentin Rothberg wrote:
> s/MMU_STD_64/STD_MMU_64/
>
> Fixes: 11ffc1cfa4c2 ("powerpc/mm/radix: Use STD_MMU_64 to properly
> isolate hash related code")
> Signed-off-by: Valentin Rothberg
> Reviewed-by: Aneesh Kumar K.V
Applied to powerp
On Mon, 2016-02-05 at 07:06:12 UTC, Alexey Kardashevskiy wrote:
> When cfg_dbg() is enabled (i.e. mapped to printk()), gcc produces
> errors as the __func__ parameter is missing (pnv_pci_cfg_read() has one);
> this adds the missing parameter. Since cfg_dbg() is used not just for
> config space acce
On Mon, 2016-02-05 at 06:00:58 UTC, Chris Smart wrote:
> The code in machine_restart/power_off/halt() includes #ifdefs around
> calls to smp_send_stop(), however these are not required as
> include/linux/smp.h includes an empty version of this function for
> CONFIG_SMP=n builds.
>
> Signed-off-by:
On Tue, 2016-12-04 at 05:33:58 UTC, Rashmica Gupta wrote:
> Support for the A2 cpu was removed in commit fb5a515704d7 ("powerpc:
> Remove platforms/wsp and associated pieces"), and the externs:
> __setup_cpu_a2 and __restore_cpu_a2 are still around and unused, so
> remove them.
>
> Signed-off-by:
On Mon, 2016-02-05 at 12:56:07 UTC, "Aneesh Kumar K.V" wrote:
> The existing usage is bogus, because we set the context.id value
> in the same function. The book3s 64 got removed in the old patch.
> Hence remove the redundant definition.
>
> Signed-off-by: Aneesh Kumar K.V
Applied to powerpc nex
On Mon, 2016-02-05 at 04:54:29 UTC, Michael Ellerman wrote:
> It's helpful for automated testing if the test returns error codes back
> to the calling program.
>
> Signed-off-by: Michael Ellerman
> Reviewed-by: Aneesh Kumar K.V
Applied to powerpc next.
https://git.kernel.org/powerpc/c/3a19e500
On Mon, 2016-02-05 at 03:51:38 UTC, Chris Smart wrote:
> Test that performing a copy paste sequence in userspace on P9 does not
> result in a leak of the copy into the paste of another process.
>
> This is based on Anton Blanchard's context_switch benchmarking code. It
> sets up two processes tied
On Wed, 4 May 2016 16:48:53 Gavin Shan wrote:
> On Wed, May 04, 2016 at 03:17:51PM +1000, Alistair Popple wrote:
> >On Tue, 3 May 2016 15:41:31 Gavin Shan wrote:
> >> This enables M64 window on P7IOC, which has been enabled on PHB3.
> >
> >Have we tested that this works with an adaptor? This looks
Excerpts from Frederic Barrat's message of 2016-05-05 00:26:09 +1000:
> I believe there's a potential problem there for powerVM guest.
> In afu_allocate_irqs(), the allocation of the bitmap for the AFU
> interrupts should return NULL (since count = 0). Therefore we'll skip
> the allocation for th
On Thu, May 05, 2016 at 09:53:51AM +1000, Alistair Popple wrote:
>On Wed, 4 May 2016 16:48:53 Gavin Shan wrote:
>> On Wed, May 04, 2016 at 03:17:51PM +1000, Alistair Popple wrote:
>> >On Tue, 3 May 2016 15:41:31 Gavin Shan wrote:
>> >> This enables M64 window on P7IOC, which has been enabled on PHB
Thanks for the clarifications Gavin. Aside from the WARN_ON() (which is not a
major thing) everything looks good.
Reviewed-By: Alistair Popple
On Thu, 5 May 2016 10:40:33 Gavin Shan wrote:
> On Thu, May 05, 2016 at 09:53:51AM +1000, Alistair Popple wrote:
> >On Wed, 4 May 2016 16:48:53 Gavin Sha
On Wed, May 04, 2016 at 11:20:01PM +1000, Gavin Shan wrote:
>On Tue, May 03, 2016 at 03:41:35PM +1000, Gavin Shan wrote:
>>In current implementation, the DMA32 segments required by one specific
>>PE isn't calculated with the information hold in the PE independently.
>>It conflicts with the PCI hotp
This enables M64 window on P7IOC, which has been enabled on PHB3.
Different from PHB3 where 16 M64 BARs are supported and each of
them can be owned by one particular PE# exclusively or divided
evenly to 256 segments, every P7IOC PHB has 16 M64 BARs and each
of them are divided to 8 segments. So eve
On 05/03/2016 03:41 PM, Gavin Shan wrote:
There are two arrays for IO and M32 segment maps on every PHB.
The index of the arrays are segment number and the value stored
in the corresponding element is PE number, indicating the segment
is assigned to the PE. Initially, all elements in those two ar
In current implementation, the DMA32 segments required by one specific
PE isn't calculated with the information hold in the PE independently.
It conflicts with the PCI hotplug design: PE centralized, meaning the
PE's DMA32 segments should be calculated from the information hold in
the PE independen
On 05/03/2016 03:41 PM, Gavin Shan wrote:
pnv_ioda_setup_pe_seg() associates the IO and M32 segments with the
owner PE. The code mapping segments should be fixed and immune from
logic changes introduced to pnv_ioda_setup_pe_seg().
This moves the code mapping segments to helper pnv_ioda_setup_pe_
On Thu, May 05, 2016 at 11:03:28AM +1000, Alistair Popple wrote:
>Thanks for the clarifications Gavin. Aside from the WARN_ON() (which is not a
>major thing) everything looks good.
>
>Reviewed-By: Alistair Popple
>
Thanks, Alistair. I'm going to send a updated revision (v10) replacing pr_warn()
w
On 05/05/2016 12:02 PM, Gavin Shan wrote:
This enables M64 window on P7IOC, which has been enabled on PHB3.
Different from PHB3 where 16 M64 BARs are supported and each of
them can be owned by one particular PE# exclusively or divided
evenly to 256 segments, every P7IOC PHB has 16 M64 BARs and ea
On 05/03/2016 03:41 PM, Gavin Shan wrote:
Currently, there is one macro (TCE32_TABLE_SIZE) representing the
TCE table size for one DMA32 segment. The constant representing
the DMA32 segment size (1 << 28) is still used in the code.
This defines PNV_IODA1_DMA32_SEGSIZE representing one DMA32
segm
On 05/03/2016 03:41 PM, Gavin Shan wrote:
Currently, the IO and M32 segments are mapped to the corresponding
PE based on the windows of the parent bridge of PE's primary bus.
It's not going to work when the windows of root port or upstream
port of the PCIe switch behind root port are extended to
On 05/03/2016 03:41 PM, Gavin Shan wrote:
This renames pcibios_{add,remove}_pci_devices() to avoid conflicts
with names of the weak functions in PCI subsystem, which have the
prefix "pcibios". No logical changes introduced.
Signed-off-by: Gavin Shan
Reviewed-by: Alexey Kardashevskiy
---
a
On 05/03/2016 03:41 PM, Gavin Shan wrote:
This moves pci_find_bus_by_node() from arch/powerpc/platforms/
pseries/pci_dlpar.c to arch/powerpc/kernel/pci-hotplug.c so that
the function can be used by pSeries and PowerNV platform at the
same time. Also, below cleanup applied. No functional changes
i
Thanks a lot, Scott and Qiang.
Will change 'DRIVER' to 'DRIVERS' and update the patchset with your acts.
Best regards,
Yangbo Lu
> -Original Message-
> From: linux-mmc-ow...@vger.kernel.org [mailto:linux-mmc-
> ow...@vger.kernel.org] On Behalf Of Scott Wood
> Sent: Thursday, May 05, 2016
This patchset is used to fix a host version register bug in the T4240-R1.0-R2.0
eSDHC controller. To get the SoC version and revision, it's needed to add the
GUTS driver to access the global utilities registers.
So, the first four patches are to add the GUTS driver.
The following patches except th
Update Freescale DCFG compatible with 'fsl,-dcfg' instead
of 'fsl,ls1021a-dcfg' to include more chips such as ls1021a,
ls1043a, and ls2080a.
Signed-off-by: Yangbo Lu
---
Changes for v8:
- Added this patch
Changes for v9:
- Added a list for the possible compatibles
Changes for v10:
Add the dts node for device configuration unit that provides
general purpose configuration and status for the device.
Signed-off-by: Yangbo Lu
Acked-by: Scott Wood
---
Changes for v5:
- Added this patch
Changes for v6:
- None
Changes for v7:
- None
Changes for v8:
The global utilities block controls power management, I/O device
enabling, power-onreset(POR) configuration monitoring, alternate
function selection for multiplexed signals,and clock control.
This patch adds GUTS driver to manage and access global utilities
block.
Signed-off-by: Yangbo Lu
Acked-
Move guts devicetree doc to Documentation/devicetree/bindings/soc/fsl/
since it's used by not only PowerPC but also ARM. And add a specification
for 'little-endian' property.
Signed-off-by: Yangbo Lu
Acked-by: Scott Wood
Acked-by: Rob Herring
---
Changes for v4:
- Added this patch
Chang
Move mpc85xx.h to include/linux/fsl and rename it to svr.h as
a common header file. It has been used for mpc85xx and it will
be used for ARM-based SoC as well.
Signed-off-by: Yangbo Lu
Acked-by: Wolfram Sang
Acked-by: Stephen Boyd
Acked-by: Scott Wood
Acked-by: Joerg Roedel
---
Changes for v2
Add maintainer entry for Freescale SoC drivers including
the QE library and the GUTS driver now. Also add maintainer
for QE library.
Signed-off-by: Yangbo Lu
Acked-by: Scott Wood
Acked-by: Qiang Zhao
---
Changes for v8:
- Added this patch
Changes for v9:
- Added linux-arm mail l
The eSDHC of T4240-R1.0-R2.0 has incorrect vender version and spec version.
Acturally the right version numbers should be VVN=0x13 and SVN = 0x1.
This patch adds the GUTS driver support for eSDHC driver to get SVR(System
version register). And fix host version to avoid that incorrect version
number
On 05/05/2016 12:04 PM, Gavin Shan wrote:
In current implementation, the DMA32 segments required by one specific
PE isn't calculated with the information hold in the PE independently.
It conflicts with the PCI hotplug design: PE centralized, meaning the
PE's DMA32 segments should be calculated fr
On Wed, 2016-05-04 at 11:24 +0800, Yangbo Lu wrote:
> -Original Message-
> From: Yangbo Lu [mailto:yangbo...@nxp.com]
> Sent: Wednesday, May 04, 2016 11:25 AM
> To: linux-...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org;
> devicet...@vger.kernel.org; linux-arm-ker...@lists.infradead.org;
On 05/03/2016 03:41 PM, Gavin Shan wrote:
This cleans up on below data struct instances to use tab instead of
space indent of statement to avoid complains from scripts/checkpatch.pl.
No logical changes introduced.
@pnv_pci_ioda_controller_ops
@pnv_npu_ioda_controller_ops
Signed-off-by: Gavi
On 05/03/2016 05:37 PM, Alistair Popple wrote:
On Fri, 29 Apr 2016 18:55:23 Alexey Kardashevskiy wrote:
The pnv_ioda_pe struct keeps an array of peers. At the moment it is only
used to link GPU and NPU for 2 purposes:
1. Access NPU quickly when configuring DMA for GPU - this was addressed
in th
On 05/04/2016 12:08 AM, Alistair Popple wrote:
Hi Alexey,
On Fri, 29 Apr 2016 18:55:24 Alexey Kardashevskiy wrote:
IBM POWER8 NVlink systems come with Tesla K40-ish GPUs each of which
also has a couple of fast speed links (NVLink). The interface to links
is exposed as an emulated PCI bridge whi
Le 05/05/2016 02:14, Ian Munsie a écrit :
Excerpts from Frederic Barrat's message of 2016-05-05 00:26:09 +1000:
I believe there's a potential problem there for powerVM guest.
In afu_allocate_irqs(), the allocation of the bitmap for the AFU
interrupts should return NULL (since count = 0). There
The zone that contains the top of memory will be either ZONE_NORMAL
or ZONE_HIGHMEM depending on the kernel config. There are two functions
in that require this information and both of them use an #ifdef to set
a local variable (top_zone). This is a little silly so lets just make it
a constant.
Si
The mm zone mechanism was traditionally used by arch specific code to
partition memory into allocation zones. However there are several zones
that are managed by the mm subsystem rather than the architecture. Most
architectures set the max PFN of these special zones to zero, however on
powerpc we s
On Tue, 2016-05-03 at 15:32 -0700, Tyrel Datwyler wrote:
> On 04/27/2016 10:34 PM, Suraj Jitindar Singh wrote:
> > diff --git a/arch/powerpc/platforms/pseries/mobility.c
> > b/arch/powerpc/platforms/pseries/mobility.c
> > index ceb18d3..a560a98 100644
> > --- a/arch/powerpc/platforms/pseries/mobil
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