On 09/04/16 16:13, Aneesh Kumar K.V wrote:
> Core kernel don't track the page size of the va range that we are
> invalidating. Hence we end up flushing tlb for the entire mm here.
> Later patches will improve this.
>
> We also don't flush page walk cache separetly instead use RIC=2 when
> flushi
On 09/04/16 16:13, Aneesh Kumar K.V wrote:
> We are going to add asm changes in the follow up patches. Add the
> feature bit now so that we can get it all build. We will enable radix
> in the last patch using cpu table.
>
> Signed-off-by: Aneesh Kumar K.V
> ---
Looks good!
Acked-by: Balbir Si
On 09/04/16 16:13, Aneesh Kumar K.V wrote:
> We also use MMU_FTR_RADIX to branch out from code path specific to
> hash.
>
> No functionality change.
>
> Signed-off-by: Aneesh Kumar K.V
> ---
> arch/powerpc/kernel/entry_64.S | 7 +--
> arch/powerpc/kernel/exceptions-64s.S | 28 +
On 09/04/16 16:13, Aneesh Kumar K.V wrote:
> On return from rtas we access the paca variables and we have 64 bit
> disabled. This requires us to limit paca in 32 bit range.
>
> Fix this by setting ppc64_rma_size to first_memblock_size/1G range.
>
> Signed-off-by: Aneesh Kumar K.V
> ---
Why is
Hi Linus,
Please pull a few powerpc fixes for 4.6:
The following changes since commit 71528d8bd7a8aa920cd69d4223c6c87d5849257d:
powerpc: Correct used_vsr comment (2016-03-29 12:08:08 +1100)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.
On 4/21/2016 4:25 PM, Christian Lamparter wrote:
On Thursday, April 21, 2016 09:15:21 PM Andy Shevchenko wrote:
The last approach in the commit 8b3444852a2b ("sata_dwc_460ex: move to generic
DMA driver") to switch to generic DMA engine API wasn't tested on bare metal.
Besides that we expecting n
On Sat, 2016-04-09 at 11:43 +0530, Aneesh Kumar K.V wrote:
> This enables us to share the same page table code for
> both radix and hash.
To be clear, only 64-bit hash.
In theory there's no reason we can't *always* mark the page tables as BE, after
all everything other than the new ppc64le syste
On Friday, April 22, 2016 06:50:44 AM Julian Margetson wrote:
> On 4/21/2016 4:25 PM, Christian Lamparter wrote:
> > On Thursday, April 21, 2016 09:15:21 PM Andy Shevchenko wrote:
> >> The last approach in the commit 8b3444852a2b ("sata_dwc_460ex: move to
> >> generic
> >> DMA driver") to switch t
On Friday, April 22, 2016 11:32:00 AM David Laight wrote:
> From: Andy Shevchenko
> > Sent: 21 April 2016 19:15
> > ata_sff_qc_issue() can't handle DMA commands and thus we have to avoid it
> > for
> > them. Do call ata_bmdma_qc_issue() instead for this case.
> >
> > Suggested-by: Christian Lampa
From: Andy Shevchenko
> Sent: 21 April 2016 19:15
> ata_sff_qc_issue() can't handle DMA commands and thus we have to avoid it for
> them. Do call ata_bmdma_qc_issue() instead for this case.
>
> Suggested-by: Christian Lamparter
> Signed-off-by: Andy Shevchenko
> ---
> drivers/ata/sata_dwc_460ex
On Tue, 2016-19-04 at 16:34:24 UTC, Frederic Barrat wrote:
> PSL designers recommend a larger value for the mmio hang pulse, 256 us
> instead of 1 us. The CAIA architecture states that it needs to be
> smaller than 1/2 of the RTOS timeout set in the PHB for outbound
> non-posted transactions, which
On Mon, 2016-21-03 at 19:32:48 UTC, Frederic Barrat wrote:
> Failure to synchronize the PSL timebase currently prevents the
> initialization of the cxl card, thus rendering the card useless. This
> is too extreme for a feature which is rarely used, if at all. No
> hardware AFUs or software is curre
On Fri, Apr 22, 2016 at 02:27:38PM +0800, Yangbo Lu wrote:
> Update Freescale DCFG compatible with 'fsl,-dcfg' instead
> of 'fsl,ls1021a-dcfg' to include more chips.
>
> Signed-off-by: Yangbo Lu
> ---
> Changes for v8:
> - Added this patch
> ---
> Documentation/devicetree/bindings/arm/fsl.
Hello.
On 04/21/2016 09:15 PM, Andy Shevchenko wrote:
The original code states:
Make sure a LLI block is not created that will span 8K max FIS
boundary. If the block spans such a FIS boundary, there is a chance
that a DMA burst will cross that boundary -- this results i
On Fri, Apr 22, 2016 at 04:37:52PM +1000, Russell Currey wrote:
>On Thu, 2016-04-21 at 21:53 +1000, Gavin Shan wrote:
>> The function eeh_pe_reset_and_recover() is used to recover EEH
>> error when the passthrou device are transferred to guest and
>> backwords. The content in the device's config sp
On Fri, Apr 22, 2016 at 04:38:45PM +1000, Russell Currey wrote:
>On Thu, 2016-04-21 at 21:53 +1000, Gavin Shan wrote:
>> The label "reset" in eeh_pe_change_owner() is used only for once.
>> No need to keep it and just drop it. No logicial changes introduced.
>
>"logicial" should be "logical". I fo
The label "reset" in eeh_pe_change_owner() is used only for once.
No need to keep it and just drop it. No logical changes introduced.
Signed-off-by: Gavin Shan
Reviewed-by: David Gibson
Reviewed-by: Russell Currey
---
arch/powerpc/kernel/eeh.c | 5 +
1 file changed, 1 insertion(+), 4 delet
The function eeh_pe_reset_and_recover() is used to recover EEH
error when the passthrou device are transferred to guest and
backwards. The content in the device's config space will be lost
on PE reset issued in the middle of the recovery. The function
saves/restores it before/after the reset. Howev
The function eeh_pe_reset_and_recover() is used to recover EEH
error when the passthrough device are transferred to guest and
backwards, meaning the device's driver is vfio-pci or none.
When the driver is vfio-pci that provides error_detected() error
handler only, the handler simply stops the guest
On Wed, Apr 13, 2016 at 01:59:14PM +1000, Michael Ellerman wrote:
> Since commit ea8daa7b9784 ("kbuild: Add option to turn incompatible
> pointer check into error"), assignments from an incompatible pointer
> types have become a hard error, eg:
>
> drivers/i2c/busses/i2c-cpm.c:545:91: error: pas
In the PowerVM environment, the PHYP CoherentAccel component manages
the state of the Coherent Accelerator Processor Interface adapter and
virtualizes CAPI resources, handles CAPP, PSL, PSL Slice errors - and
interrupts - and provides a new set of hcalls for the OS APIs to utilize
Accelerator Funct
On Fri, Apr 22, 2016 at 08:47:56AM +1000, Benjamin Herrenschmidt wrote:
> On Wed, 2016-04-20 at 03:58 -0400, Aneesh Kumar K.V wrote:
> > The driver was requesting for a writethrough mapping. But with thoses
> > flags we will end up with a SAO mapping because we now have memory
> > conherence always
On Fri, 2016-04-22 at 14:27 +0800, Yangbo Lu wrote:
> Add maintainer entry for Freescale SoC specific driver including
> the QE library and the GUTS driver. Also add entry for GUTS driver
> and add maintainer for QE library.
>
> Signed-off-by: Yangbo Lu
> ---
> Changes for v8:
> - Added thi
Hello devs,
during my testing on ppc hardware im facing issue with xorgs and radeon hd
on varisys/Aeon Cyrus+ P5020 machine and on Quad G5 hardware too.
On Quad G5 with 2 video boards
if i set radeon.modeset=1 nouveau.modeset=1 Xorg -configure dont found at all
the video boards
if i set radeo
Hi Stewart,
On 04/20/2016 03:41 AM, Stewart Smith wrote:
Akshay Adiga writes:
Iozone results show fairly consistent performance boost.
YCSB on redis shows improved Max latencies in most cases.
What about power consumption?
Iozone write/rewite test were made with filesizes 200704Kb and 40140
Hello Petr,
On (04/21/16 13:48), Petr Mladek wrote:
> extern void printk_nmi_flush(void);
> +extern void printk_nmi_flush_on_panic(void);
> #else
> static inline void printk_nmi_flush(void) { }
> +static inline void printk_nmi_flush_on_panic(void) { }
[..]
> +void printk_nmi_flush_on_panic(void
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