> -邮件原件-
> 发件人: Viresh Kumar [mailto:viresh.ku...@linaro.org]
> 发送时间: Monday, April 18, 2016 6:33 PM
> 收件人: Hongtao Jia
> 抄送: linux...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org; Scott Wood
> ; Yuantian Tang
> 主题: Re: [PATCH 1/2] cpufreq: qoriq: Fix cooling device registration issue
Thanks for addressing my feedback :)
Reviewed-by: Ian Munsie
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On 19-04-16, 14:43, Jia Hongtao wrote:
> Cooling device is registered by ready callback. It's also invoked while
> system resuming from sleep (Enabling non-boot cpus). Thus cooling device
> may be multiple registered. Matchable unregistration is added to exit
> callback to fix this issue.
>
> Sign
On 02/17/2016 02:44 PM, Gavin Shan wrote:
The pdn (struct pci_dn) instances are allocated from memblock or
bootmem when creating PCI controller (hoses) in setup_arch(). PCI
hotplug, which will be supported by proceeding patches, releases
PCI device nodes and their corresponding pdn on unplugging
On 02/17/2016 02:44 PM, Gavin Shan wrote:
In hotplug case, function pci_add_pci_devices() is called to rescan
the specified PCI bus, which might not have any child devices. Access
to the PCI bus's child device node will cause kernel crash without
exception.
This adds one more check to skip scann
Hi Scott,
Thanks for reviewing it!
On 19 April 2016 at 06:26, Scott Wood wrote:
> On Mon, 2016-04-18 at 09:57 +0200, Alessio Igor Bogani wrote:
>> + pci0: pcie@f1008000 {
>> + reg = <0xf1008000 0x1000>;
>> + ranges = <0x0200 0x0 0x8000 0x8000 0x0
>> 0x5000
On Mon, 2016-04-18 at 14:54 -0700, bruce_leon...@selinc.com wrote:
>
> On the DMA transactions that work, the virtual address I hand to
> dma_map_single() is something like 0xe084 and the dma_addr_t result is
> 0x1084 which is less than my 512Mb limit. On the transactions that
> don't
On 02/17/2016 02:44 PM, Gavin Shan wrote:
On the PCI plugging event, PCI slot's subordinate devices are
scanned and their (IO and MMIO) resources are assigned. Platform
dependent resources (PE#, IO/MMIO/DMA windows) are allocated or
created on updating windows of the slot's upstream bridge.
This
On 02/17/2016 02:44 PM, Gavin Shan wrote:
This drops unnecessary nested if statements in pnv_eeh_reset() to
improve the code readability. After the changes, the unused local
variable "ret" is dropped as well. No logical changes introduced.
Signed-off-by: Gavin Shan
Reviewed-by: Alexey Karda
On 02/17/2016 02:44 PM, Gavin Shan wrote:
The function pnv_pci_reset_secondary_bus() is called like below.
It's impossible for call the function on root bus. So it's safe
to remove the root bus case in the function. No functional changes
introduced.
pci_parent_bus_reset() / pci_bus_reset() /
On 02/17/2016 02:44 PM, Gavin Shan wrote:
In pnv_pci_reset_secondary_bus(), we should issue fundamental reset
if any one subordinate device of the specified bus is requesting that.
Otherwise, the device might not come up after the reset.
Signed-off-by: Gavin Shan
Reviewed-by: Alexey Kardashe
> -邮件原件-
> 发件人: Viresh Kumar [mailto:viresh.ku...@linaro.org]
> 发送时间: Tuesday, April 19, 2016 3:54 PM
> 收件人: Hongtao Jia
> 抄送: linux...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org; Scott Wood
> ; Yuantian Tang
> 主题: Re: [PATCH V2] cpufreq: qoriq: Fix cooling device registration issue
On 19-04-16, 17:00, Jia Hongtao wrote:
> .exit callback (qoriq_cpufreq_cpu_exit()) is also used during suspend.
> So __exit macro should be removed or the function will be discarded.
>
> Signed-off-by: Jia Hongtao
> ---
> drivers/cpufreq/qoriq-cpufreq.c | 4 ++--
> 1 file changed, 2 insertions(+
On 19-04-16, 17:00, Jia Hongtao wrote:
> Cooling device is registered by ready callback. It's also invoked while
> system resuming from sleep (Enabling non-boot cpus). Thus cooling device
> may be multiple registered. Matchable unregistration is added to exit
> callback to fix this issue.
>
> Sign
On 19/04/2016 04:40, Andrew Donnellan wrote:
On 18/04/16 23:05, Christophe Lombard wrote:
In the POWERVM environement, the PHYP CoherentAccel component manages
environment
the state of the Coherant Accelerator Processor Interface adapter and
Coherent
virtualizes CAPI resources, handles C
Hi Xinhui,
On Tue, Apr 19, 2016 at 02:29:34PM +0800, Pan Xinhui wrote:
> From: Pan Xinhui
>
> Implement xchg{u8,u16}{local,relaxed}, and
> cmpxchg{u8,u16}{,local,acquire,relaxed}.
>
> It works on all ppc.
>
Nice work!
AFAICT, your work doesn't depend on anything that ppc-specific, right?
So
Cooling device is registered by ready callback. It's also invoked while
system resuming from sleep (Enabling non-boot cpus). Thus cooling device
may be multiple registered. Matchable unregistration is added to exit
callback to fix this issue.
Signed-off-by: Jia Hongtao
---
drivers/cpufreq/qoriq-
On 02/17/2016 02:44 PM, Gavin Shan wrote:
PowerNV platforms runs on top of skiboot firmware that includes
changes to support PCI slots. PCI slots are identified by PHB's
ID or the combo of that and PCI slot ID.
This changes the EEH PowerNV backend to support PCI slots:
* Rename arguments of
On 02/17/2016 02:44 PM, Gavin Shan wrote:
The skiboot firmware might provide the PCI slot reset capability
which is identified by property "ibm,reset-by-firmware" on the
PCI slot associated device node.
This checks the property. If it exists, the reset request is routed
to firmware. Otherwise, t
Now that the FMAN mac driver has been merged the fman node is relevant.
The kmcoge4 board implements 3 ethernet interfaces, 1 with a RGMII phy
and 2 with fixed 1 Giga SGMII links.
Signed-off-by: Valentin Longchamp
---
arch/powerpc/boot/dts/fsl/kmcoge4.dts | 37 ++
On 02/17/2016 02:44 PM, Gavin Shan wrote:
This exports 4 functins, which base on the corresponding OPAL
s/functins/functions/
APIs to get/set PCI slot status. Those functions are going to
be used by PowerNV PCI hotplug driver:
pnv_pci_get_device_tree()opal_get_device_tree()
pnv
On 02/17/2016 02:44 PM, Gavin Shan wrote:
The device tree will change dynamically in PowerNV PCI hotplug
driver. This enables CONFIG_OF_DYNAMIC to support that.
Signed-off-by: Gavin Shan
---
arch/powerpc/platforms/powernv/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/power
.exit callback (qoriq_cpufreq_cpu_exit()) is also used during suspend.
So __exit macro should be removed or the function will be discarded.
Signed-off-by: Jia Hongtao
---
drivers/cpufreq/qoriq-cpufreq.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/cpufreq/qoriq
On Mon, 2016-04-18 at 15:05 +0200, Christophe Lombard wrote:
> In the POWERVM environement, the PHYP CoherentAccel component manages
PowerVM is correct I think.
> the state of the Coherant Accelerator Processor Interface adapter and
^
Hi Viresh,
On 04/18/2016 03:48 PM, Viresh Kumar wrote:
On 15-04-16, 11:58, Akshay Adiga wrote:
static int powernv_cpufreq_reboot_notifier(struct notifier_block *nb,
- unsigned long action, void *unused)
+ unsigned long act
From: Shilpasri G Bhat
commit 1b0289848d5d ("cpufreq: powernv: Add sysfs attributes to show
throttle stats") used policy->driver_data as a flag for one-time creation
of throttle sysfs files. Instead of this use 'kernfs_find_and_get()' to
check if the attribute already exists. This is required as
The frequency transition latency from pmin to pmax is observed to be in few
millisecond granurality. And it usually happens to take a performance penalty
during sudden frequency rampup requests.
This patch set solves this problem by using a chip-level entity called "global
pstates". Global pstate
The frequency transition latency from pmin to pmax is observed to be in
few millisecond granurality. And it usually happens to take a performance
penalty during sudden frequency rampup requests.
This patch set solves this problem by using an entity called "global
pstates". The global pstate is a C
On Mon, 2016-18-04 at 10:36:07 UTC, Michael Ellerman wrote:
> From: Anton Blanchard
>
> The REAL_LE feature entry in the ibm_pa_feature struct is missing an MMU
> feature value, meaning all the remaining elements initialise the wrong
> values.
...
>
> Fix the code by adding the missing initialis
On Fri, 2016-15-04 at 02:07:24 UTC, Unknown sender due to SPF wrote:
> scan_features() updates cpu_user_features but not cpu_user_features2.
>
> Amongst other things, cpu_user_features2 contains the user TM feature
> bits which we must keep in sync with the kernel TM feature bit.
>
> Signed-off-b
On Fri, 2016-15-04 at 02:08:19 UTC, Unknown sender due to SPF wrote:
> We need to update the user TM feature bits (PPC_FEATURE2_HTM and
> PPC_FEATURE2_HTM) to mirror what we do with the kernel TM feature
> bit.
>
> At the moment, if firmware reports TM is not available we turn off
> the kernel TM
On Wed, 2016-13-04 at 12:53:19 UTC, Michael Ellerman wrote:
> In order to support live patching on powerpc we would like to call
> ftrace_location_range(), so make it global.
>
> Signed-off-by: Torsten Duwe
> Signed-off-by: Balbir Singh
> Signed-off-by: Michael Ellerman
Applied to powerpc next
On Wed, 2016-13-04 at 12:53:20 UTC, Michael Ellerman wrote:
> When livepatch tries to patch a function it takes the function address
> and asks ftrace to install the livepatch handler at that location.
> ftrace will look for an mcount call site at that exact address.
>
> On powerpc the mcount loca
On Wed, 2016-13-04 at 12:53:21 UTC, Michael Ellerman wrote:
> Add the powerpc specific livepatch definitions. In particular we provide
> a non-default implementation of klp_get_ftrace_location().
>
> This is required because the location of the mcount call is not constant
> when using -mprofile-ke
On Wed, 2016-13-04 at 12:53:22 UTC, Michael Ellerman wrote:
> In order to support live patching we need to maintain an alternate
> stack of TOC & LR values. We use the base of the stack for this, and
> store the "live patch stack pointer" in struct thread_info.
>
> Unlike the other fields of threa
On Wed, 2016-13-04 at 12:53:23 UTC, Michael Ellerman wrote:
> Add the kconfig logic & assembly support for handling live patched
> functions. This depends on DYNAMIC_FTRACE_WITH_REGS, which in turn
> depends on the new -mprofile-kernel ftrace ABI, which is only supported
> currently on ppc64le.
...
On 02/17/2016 02:44 PM, Gavin Shan wrote:
This adds standalone driver to support PCI hotplug for PowerPC PowerNV
platform that runs on top of skiboot firmware. The firmware identifies
hotpluggable slots and marked their device tree node with proper
"ibm,slot-pluggable" and "ibm,reset-by-firmware"
On 2016/4/18 19:30, David Laight wrote:
From: Yongji Xie
Sent: 18 April 2016 11:59
We introduce a new pci_bus_flags, PCI_BUS_FLAGS_MSI_REMAP
which indicates all devices on the bus are protected by the
hardware which supports IRQ remapping(intel naming).
This flag will be used to know whether it
Add a check for p->state == TASK_RUNNING so that any wake-ups on
task_struct p in the interim lead to 0 being returned by get_wchan().
Signed-off-by: Kautuk Consul
---
arch/powerpc/kernel/process.c |3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/kernel/proce
Wire up preadv2/pwritev2 in the same way as preadv/pwritev. Fixes two
build warnings on ppc64.
Signed-off-by: Rui Salvaterra
---
arch/powerpc/include/asm/systbl.h | 2 ++
arch/powerpc/include/asm/unistd.h | 2 +-
arch/powerpc/include/uapi/asm/unistd.h | 2 ++
3 files changed, 5 inserti
On 04/19/2016 04:27 AM, Ian Munsie wrote:
Thanks for addressing my feedback :)
Reviewed-by: Ian Munsie
Thanks very much for reviewing Ian =)
Cheers,
Guilherme
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On 03/15/2016 12:15 AM, linuxppc-dev-requ...@lists.ozlabs.org wrote:
> Documentation/devicetree/bindings ? or link to PAPR where it's specified?
>
> --
> Stewart Smith
< OPAL Architect, IBM.
Here's the link to the Notes PAPR database's issue:
notes://D01DBR12/86256680004635D2/565907e362ce41e
Michael Ellerman writes:
> On Fri, 2016-19-02 at 05:38:47 UTC, Rashmica Gupta wrote:
>> Currently on PPC64 changing kernel pagesize from 4K to 64K leaves
>> FORCE_MAX_ZONEORDER set to 13 - which produces a compile error.
>>
> ...
>> So, update the range of FORCE_MAX_ZONEORDER from 9-64 to 8-9 fo
Le 30/03/2016 10:50, Zhao Qiang a écrit :
The driver add hdlc support for Freescale QUICC Engine.
It support NMSI and TSA mode.
When using TSA, how does the TSA gets configured ? Especially how do you
describe which Timeslot is switched to HDLC channels ?
Is it possible to route some Timeslots t
PSL designers recommend a larger value for the mmio hang pulse, 256 us
instead of 1 us. The CAIA architecture states that it needs to be
smaller than 1/2 of the RTOS timeout set in the PHB for outbound
non-posted transactions, which is still (easily) the case here.
Signed-off-by: Frederic Barrat
Ben,
Benjamin Herrenschmidt wrote on 04/19/2016 01:45:40 AM:
> From: Benjamin Herrenschmidt
> To: bruce_leon...@selinc.com, linuxppc-dev@lists.ozlabs.org
> Date: 04/19/2016 01:46 AM
> Subject: Re: Trouble with DMA on PPC linux question
>
> On Mon, 2016-04-18 at 14:54 -0700, bruce_leon...@selin
On Tue, 2016-04-19 at 10:33 +0200, Alessio Igor Bogani wrote:
> Hi Scott,
>
> Thanks for reviewing it!
>
> On 19 April 2016 at 06:26, Scott Wood wrote:
> > On Mon, 2016-04-18 at 09:57 +0200, Alessio Igor Bogani wrote:
> > > + pci0: pcie@f1008000 {
> > > + reg = <0xf1008000 0x1000
On 16/04/16 01:07, Jiri Kosina wrote:
> On Thu, 14 Apr 2016, Michael Ellerman wrote:
>
>> Topic branch here:
>>
>>
>> https://git.kernel.org/cgit/linux/kernel/git/powerpc/linux.git/log/?h=topic/livepatch
>>
>> I will merge that before Monday (my time) if I don't hear any objections.
>
> I've
On Wed, 20 Apr 2016, Balbir Singh wrote:
> Thanks, do we have a summary of what the relocation changes look like?
This work is queued in
livepatching.git#for-4.7/arch-independent-klp-relocations
--
Jiri Kosina
SUSE Labs
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On 20/04/16 00:59, Aneesh Kumar K.V wrote:
> Michael Ellerman writes:
>
>> On Fri, 2016-19-02 at 05:38:47 UTC, Rashmica Gupta wrote:
>>> Currently on PPC64 changing kernel pagesize from 4K to 64K leaves
>>> FORCE_MAX_ZONEORDER set to 13 - which produces a compile error.
>>>
>> ...
>>> So, updat
On Wed, Apr 13, 2016 at 03:52:25PM +1000, Alexey Kardashevskiy wrote:
>On 02/17/2016 02:43 PM, Gavin Shan wrote:
>>Each PHB has one instance of "struct pci_controller_ops", which
>>includes various callbacks called by PCI subsystem. In the definition
>>of this struct, some callbacks have explicit n
On Wed, Apr 13, 2016 at 04:45:39PM +1000, Alexey Kardashevskiy wrote:
>On 02/17/2016 02:43 PM, Gavin Shan wrote:
>>The original implementation of pnv_ioda_setup_pe_seg() configures
>>IO and M32 segments by separate logics, which can be merged by
>>by caching @segmap, @seg_size, @win in advance. Thi
On Wed, Apr 13, 2016 at 05:09:45PM +1000, Alexey Kardashevskiy wrote:
>On 02/17/2016 02:43 PM, Gavin Shan wrote:
>>When unplugging PCI devices, their parent PEs might be offline.
>>The consumed M64 resource by the PEs should be released at that
>>time. As we track M32 segment consumption, this intr
On Wed, Apr 13, 2016 at 05:47:59PM +1000, Alexey Kardashevskiy wrote:
>On 02/17/2016 02:43 PM, Gavin Shan wrote:
>>This enables M64 window on P7IOC, which has been enabled on PHB3.
>>Different from PHB3 where 16 M64 BARs are supported and each of
>>them can be owned by one particular PE# exclusivel
On Wed, Apr 13, 2016 at 06:59:40PM +1000, Alexey Kardashevskiy wrote:
>On 02/17/2016 02:43 PM, Gavin Shan wrote:
>>PEs are put into PHB DMA32 list (phb->ioda.pe_dma_list) according
>>to their DMA32 weight. The PEs on the list are iterated to setup
>>their TCE32 tables at system booting time. The li
On Tue, Apr 19, 2016 at 11:50:10AM +1000, Alexey Kardashevskiy wrote:
>On 02/17/2016 02:44 PM, Gavin Shan wrote:
>>In current implementation, the DMA32 segments required by one specific
>>PE isn't calculated with the information hold in the PE independently.
>>It conflicts with the PCI hotplug desi
On Tue, Apr 19, 2016 at 12:02:23PM +1000, Alexey Kardashevskiy wrote:
>On 02/17/2016 02:44 PM, Gavin Shan wrote:
>>Each PHB maintains an array helping to translate 2-bytes Request
>>ID (RID) to PE# with the assumption that PE# takes one byte, meaning
>>that we can't have more than 256 PEs. However,
On Tue, Apr 19, 2016 at 01:07:59PM +1000, Alexey Kardashevskiy wrote:
>On 02/17/2016 02:44 PM, Gavin Shan wrote:
>>PE number for one particular PE can be allocated dynamically or
>>reserved according to the consumed M64 (64-bits prefetchable)
>>segments of the PE. The M64 resources, and hence their
On Tue, Apr 19, 2016 at 02:16:42PM +1000, Alexey Kardashevskiy wrote:
>On 02/17/2016 02:44 PM, Gavin Shan wrote:
>>Currently, the PEs and their associated resources are assigned
>>in ppc_md.pcibios_fixup() except those used by SRIOV VFs.
>
>But this new code does not affect IOV and VF's PEs will st
On Tue, Apr 19, 2016 at 02:28:51PM +1000, Alexey Kardashevskiy wrote:
>On 02/17/2016 02:44 PM, Gavin Shan wrote:
>>pnv_pci_ioda_table_free_pages() can be reused to release the IODA1
>>TCE table when releasing IODA1 PE in subsequent patches.
>>
>>This renames the following functions to support relea
On Tue, Apr 19, 2016 at 03:28:36PM +1000, Alexey Kardashevskiy wrote:
>On 02/17/2016 02:44 PM, Gavin Shan wrote:
>>This renames pcibios_{add,remove}_pci_devices() to avoid conflicts
>>with names of the weak functions in PCI subsystem, which have the
>>prefix "pcibios". No logical changes introduced
On Tue, Apr 19, 2016 at 03:48:26PM +1000, Alexey Kardashevskiy wrote:
>On 02/17/2016 02:44 PM, Gavin Shan wrote:
>>This implements and exports pci_remove_device_node_info(). It's
>>used to remove the pdn (struct pci_dn) for the indicated device
>>node. The function is going to be used by PowerNV PC
On Tue, Apr 19, 2016 at 03:51:03PM +1000, Alexey Kardashevskiy wrote:
>On 02/17/2016 02:44 PM, Gavin Shan wrote:
>>This renames traverse_pci_devices() to pci_traverse_device_nodes().
>>The function traverses all subordinate device nodes of the specified
>>one. Also, below cleanup applied to the fun
This flag is a no-op now (see commit 47b0eeb3dc8a "clk: Deprecate
CLK_IS_ROOT", 2016-02-02) so remove it.
Cc: Gerhard Sittig
Signed-off-by: Stephen Boyd
---
arch/powerpc/platforms/512x/clock-commonclk.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/platforms/5
Acked-by: Ian Munsie
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On Tue, Apr 19, 2016 at 07:04:19PM +1000, Alexey Kardashevskiy wrote:
>On 02/17/2016 02:44 PM, Gavin Shan wrote:
>>In pnv_pci_reset_secondary_bus(), we should issue fundamental reset
>>if any one subordinate device of the specified bus is requesting that.
>>Otherwise, the device might not come up a
On Tue, 19 Apr 2016 20:36:48 Alexey Kardashevskiy wrote:
> On 02/17/2016 02:44 PM, Gavin Shan wrote:
> > This adds standalone driver to support PCI hotplug for PowerPC PowerNV
> > platform that runs on top of skiboot firmware. The firmware identifies
> > hotpluggable slots and marked their device t
On Tue, Apr 19, 2016 at 06:19:20PM +1000, Alexey Kardashevskiy wrote:
>On 02/17/2016 02:44 PM, Gavin Shan wrote:
>>The pdn (struct pci_dn) instances are allocated from memblock or
>>bootmem when creating PCI controller (hoses) in setup_arch(). PCI
>>hotplug, which will be supported by proceeding pa
On Tue, Apr 19, 2016 at 07:28:20PM +1000, Alexey Kardashevskiy wrote:
>On 02/17/2016 02:44 PM, Gavin Shan wrote:
>>PowerNV platforms runs on top of skiboot firmware that includes
>>changes to support PCI slots. PCI slots are identified by PHB's
>>ID or the combo of that and PCI slot ID.
>>
>>This c
On Tue, Apr 19, 2016 at 07:34:55PM +1000, Alexey Kardashevskiy wrote:
>On 02/17/2016 02:44 PM, Gavin Shan wrote:
>>The skiboot firmware might provide the PCI slot reset capability
>>which is identified by property "ibm,reset-by-firmware" on the
>>PCI slot associated device node.
>>
>>This checks th
On Tue, Apr 19, 2016 at 07:39:34PM +1000, Alexey Kardashevskiy wrote:
>On 02/17/2016 02:44 PM, Gavin Shan wrote:
>>This exports 4 functins, which base on the corresponding OPAL
>
>
>s/functins/functions/
>
Thanks.
>>APIs to get/set PCI slot status. Those functions are going to
>>be used by PowerN
On Fri, Apr 15, 2016 at 11:10:21AM -0500, Rob Herring wrote:
>On Wed, Apr 13, 2016 at 8:30 PM, Gavin Shan wrote:
>> On Thu, Apr 14, 2016 at 09:57:32AM +1000, Alistair Popple wrote:
>>>Hi Gavin,
>>>
>>>
>>>
>Why exactly cannot EEH reset changes go to a smaller separate patchset
>(before h
On 20/04/2016 12:22AM, Christophe Leroy wrote
> -Original Message-
> From: Christophe Leroy [mailto:christophe.le...@c-s.fr]
> Sent: Wednesday, April 20, 2016 12:22 AM
> To: Qiang Zhao ; da...@davemloft.net
> Cc: gre...@linuxfoundation.org; Xiaobo Xie ; linux-
> ker...@vger.kernel.org; o..
On 04/20/2016 10:22 AM, Gavin Shan wrote:
On Wed, Apr 13, 2016 at 05:47:59PM +1000, Alexey Kardashevskiy wrote:
On 02/17/2016 02:43 PM, Gavin Shan wrote:
This enables M64 window on P7IOC, which has been enabled on PHB3.
Different from PHB3 where 16 M64 BARs are supported and each of
them can be
On Wed, Feb 17, 2016 at 08:30:42AM -0600, Rob Herring wrote:
>On Tue, Feb 16, 2016 at 9:44 PM, Gavin Shan wrote:
>> The function unflatten_dt_node() is called recursively to unflatten
>> device nodes and properties in the FDT blob. It looks complicated
>> and hard to be understood.
>>
>> This spli
On Sat, 2016-09-04 at 06:14:04 UTC, "Aneesh Kumar K.V" wrote:
> We can depend on ibm,pa-features to enable/disable radix. This gives us
> a nice way to test p9 hash config, by changing device tree property.
I think we might want to be more careful here.
You set MMU_FTR_RADIX in the cputable entry
On 04/20/2016 11:12 AM, Gavin Shan wrote:
On Tue, Apr 19, 2016 at 02:16:42PM +1000, Alexey Kardashevskiy wrote:
On 02/17/2016 02:44 PM, Gavin Shan wrote:
Currently, the PEs and their associated resources are assigned
in ppc_md.pcibios_fixup() except those used by SRIOV VFs.
But this new code
On Wed, 2016-04-13 at 08:12 +0530, Aneesh Kumar K.V wrote:
> "Aneesh Kumar K.V" writes:
> > Also note that the `~` operation is wrong.
> >
> > Cc: Frederic Barrat
> > Cc: Andrew Donnellan
> > Acked-by: Ian Munsie
> > Signed-off-by: Aneesh Kumar K.V
> > ---
> > drivers/misc/cxl/fault.c | 2 +-
On Tue, Apr 19, 2016 at 07:42:01PM +1000, Alexey Kardashevskiy wrote:
>On 02/17/2016 02:44 PM, Gavin Shan wrote:
>>The device tree will change dynamically in PowerNV PCI hotplug
>>driver. This enables CONFIG_OF_DYNAMIC to support that.
>>
>>Signed-off-by: Gavin Shan
>>---
>> arch/powerpc/platform
On 04/20/2016 11:15 AM, Gavin Shan wrote:
On Tue, Apr 19, 2016 at 02:28:51PM +1000, Alexey Kardashevskiy wrote:
On 02/17/2016 02:44 PM, Gavin Shan wrote:
pnv_pci_ioda_table_free_pages() can be reused to release the IODA1
TCE table when releasing IODA1 PE in subsequent patches.
This renames the
On 04/20/2016 11:23 AM, Gavin Shan wrote:
On Tue, Apr 19, 2016 at 03:28:36PM +1000, Alexey Kardashevskiy wrote:
On 02/17/2016 02:44 PM, Gavin Shan wrote:
This renames pcibios_{add,remove}_pci_devices() to avoid conflicts
with names of the weak functions in PCI subsystem, which have the
prefix "
On Wed, Apr 20, 2016 at 01:00:38PM +1000, Alexey Kardashevskiy wrote:
>On 04/20/2016 11:12 AM, Gavin Shan wrote:
>>On Tue, Apr 19, 2016 at 02:16:42PM +1000, Alexey Kardashevskiy wrote:
>>>On 02/17/2016 02:44 PM, Gavin Shan wrote:
Currently, the PEs and their associated resources are assigned
>>
On 04/20/2016 11:27 AM, Gavin Shan wrote:
On Tue, Apr 19, 2016 at 03:51:03PM +1000, Alexey Kardashevskiy wrote:
On 02/17/2016 02:44 PM, Gavin Shan wrote:
This renames traverse_pci_devices() to pci_traverse_device_nodes().
The function traverses all subordinate device nodes of the specified
one.
Hello, boqun
On 2016年04月19日 17:18, Boqun Feng wrote:
> Hi Xinhui,
>
> On Tue, Apr 19, 2016 at 02:29:34PM +0800, Pan Xinhui wrote:
>> From: Pan Xinhui
>>
>> Implement xchg{u8,u16}{local,relaxed}, and
>> cmpxchg{u8,u16}{,local,acquire,relaxed}.
>>
>> It works on all ppc.
>>
>
> Nice work!
>
tha
On 04/20/2016 12:13 PM, Gavin Shan wrote:
On Tue, Apr 19, 2016 at 06:19:20PM +1000, Alexey Kardashevskiy wrote:
On 02/17/2016 02:44 PM, Gavin Shan wrote:
The pdn (struct pci_dn) instances are allocated from memblock or
bootmem when creating PCI controller (hoses) in setup_arch(). PCI
hotplug, w
Em Mon, Apr 18, 2016 at 03:17:11PM +0530, Anju T escreveu:
> On Saturday 20 February 2016 10:32 AM, Anju T wrote:
> >This short patch series adds the ability to sample the interrupted
> >machine state for each hardware sample.
> >
> >To test this patchset,
> >Eg:
> >
> >$ perf record -I? # li
On Sat, 2016-09-04 at 06:12:58 UTC, "Aneesh Kumar K.V" wrote:
> if it is a hugetlb address return without calling __flush_tlb_page.
Why?
cheers
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On 04/20/2016 12:28 PM, Gavin Shan wrote:
On Tue, Apr 19, 2016 at 07:28:20PM +1000, Alexey Kardashevskiy wrote:
On 02/17/2016 02:44 PM, Gavin Shan wrote:
PowerNV platforms runs on top of skiboot firmware that includes
changes to support PCI slots. PCI slots are identified by PHB's
ID or the com
On 04/20/2016 12:33 PM, Gavin Shan wrote:
On Tue, Apr 19, 2016 at 07:34:55PM +1000, Alexey Kardashevskiy wrote:
On 02/17/2016 02:44 PM, Gavin Shan wrote:
The skiboot firmware might provide the PCI slot reset capability
which is identified by property "ibm,reset-by-firmware" on the
PCI slot asso
On 04/20/2016 12:36 PM, Gavin Shan wrote:
On Tue, Apr 19, 2016 at 07:39:34PM +1000, Alexey Kardashevskiy wrote:
On 02/17/2016 02:44 PM, Gavin Shan wrote:
This exports 4 functins, which base on the corresponding OPAL
s/functins/functions/
Thanks.
APIs to get/set PCI slot status. Those fu
On Wed, 2016-04-20 at 00:57 -0300, Arnaldo Carvalho de Melo wrote:
> Em Mon, Apr 18, 2016 at 03:17:11PM +0530, Anju T escreveu:
> > On Saturday 20 February 2016 10:32 AM, Anju T wrote:
> > >
> > > arch/powerpc/Kconfig| 1 +
> > > arch/powerpc/include/uapi/asm/perf_regs.h
On 04/20/2016 10:49 AM, Gavin Shan wrote:
On Tue, Apr 19, 2016 at 11:50:10AM +1000, Alexey Kardashevskiy wrote:
On 02/17/2016 02:44 PM, Gavin Shan wrote:
In current implementation, the DMA32 segments required by one specific
PE isn't calculated with the information hold in the PE independently.
There is an ordering issue with spin_unlock_wait() on powerpc, because
the spin_lock primitive is an ACQUIRE and an ACQUIRE is only ordering
the load part of the operation with memory operations following it.
Therefore the following event sequence can happen:
CPU 1 CPU 2
>>> + if (htab_bolt_mapping(ea, ea + PAGE_SIZE, pa, flags,
>>> + mmu_io_psize, mmu_kernel_ssize)) {
>>> + printk(KERN_ERR "Failed to do bolted mapping IO "
>>> + "memory at %016lx !\n", pa);
>>> +
On 17/04/16 20:27, Aneesh Kumar K.V wrote:
> Balbir Singh writes:
>
>>> index 2f818cbd8aa6..dcb9d6e94a0c 100644
>>> --- a/arch/powerpc/include/asm/book3s/64/hash-4k.h
>>> +++ b/arch/powerpc/include/asm/book3s/64/hash-4k.h
>>> @@ -5,48 +5,20 @@
>>> * for each page table entry. The PMD and PGD
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