This enables us to share the same page table code for
both radix and hash. Radix use a hardware defined big endian
page table
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/hash.h | 16 +++--
arch/powerpc/include/asm/kvm_book3s_64.h| 13 ++--
arch/powerpc/include/
This split _PAGE_RW bit to _PAGE_READ and _PAGE_WRITE. It also remove
the dependency on _PAGE_USER for implying read only. Few things to note
here is that, we have read implied with write and execute permission.
Hence we should always find _PAGE_READ set on hash pte fault.
We still can't switch PR
We have common declaration in pte-common.h Add book3s specific one
and switch to pte_user. In the later patch we will be switching
_PAGE_USER to _PAGE_PRIVILEGED
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/pgtable.h | 5 +
arch/powerpc/perf/callchain.c
_PAGE_PRIVILEGED means the page can be accessed only by kernel. This is done
to keep pte bits similar to PowerISA 3.0 radix PTE format. User
pages are now makred by clearing _PAGE_PRIVILEGED bit.
Previously we allowed kernel to have a privileged page
in the lower address range(USER_REGION). With t
Subpage protection used to depend on _PAGE_USER bit to implement no
access mode. This patch switch that to use _PAGE_RWX. We clear READ,
Write and Execute access from pte instead of clearing _PAGE_USER now.
This was done so that we can switch to _PAGE_PRIVILEGED in later patch.
subpage_protection()
Signed-off-by: Aneesh Kumar K.V
---
drivers/misc/cxl/fault.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/misc/cxl/fault.c b/drivers/misc/cxl/fault.c
index 33bd0ee30edd..67cc657e96cc 100644
--- a/drivers/misc/cxl/fault.c
+++ b/drivers/misc/cxl/fault.c
@@ -154,7 +154
PTE_RPN_SHIFT is actually page size dependent. Even tough PowerISA 3.0
expect only lower 12 bits to be zero, we will always find the pages to
be PAGE_SHIFT aligned. In case of hash config, this also allows us to
use the additional 3 bits to track pte specific information. We need
to make sure we us
PS3 had used PPP bit hack to implement a read only mapping in the
kernel area. Since we are bolt mapping the ioremap area, it used
the pte flags _PAGE_PRESENT | _PAGE_USER to get a PPP value of 0x3
there by resulting in a read only mapping. This means the area
can be accessed by user space, but ker
Use helper instead of opencoding with constants. Later patch will
drop the WIMG bits and use PowerISA 3.0 defines
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/kernel/btext.c | 2 +-
arch/powerpc/kernel/isa-bridge.c | 4 ++--
arch/powerpc/kernel/pci_64.c | 2 +-
arch/powerpc/mm/pgtab
PowerISA 3.0 introduce two pte bits with the below meaning w.r.t Radix
00 -> Normal Memory
01 -> Strong Access Order
10 -> Non idempotent I/O (Cache inhibited and guarded)
11 -> Tolerant I/O (Cache inhibited)
We drop the existing WIMG bits in linux page table in favour of above
constants. We loo
The radix variant is going to require a flush_pmd_tlb_range. With
flush_pmd_tlb_range added, pmdp_clear_flush_young is same as the generic
version. So drop the powerpc specific variant
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/pgtable.h | 3 ---
arch/powerpc/mm/pgta
The radix variant is going to require a flush_tlb_range. With
flush_tlb_range added, ptep_clear_flush_young is same as the generic
version. So drop the powerpc specific variant
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/hash.h | 23 +++
1 file chan
We want to use mmu_context_t with radix and hash. Move that mmuh.h
With this patch, we start moving code that is generic between radix
and hash to book3s specific headers from book3s hash 64 specific one.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/32/mmu-hash.h | 6 +--
We also add mach dep call back for updating partition table entry.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/mmu.h | 31 +--
arch/powerpc/include/asm/machdep.h | 1 +
arch/powerpc/include/asm/reg.h | 1 +
3 files changed,
PowerISA 3.0 adds a parition table indexed by LPID. Parition table allow
us to specify the MMU model that will be used for guest and host
translation.
This patch add support with SLB based hash model (UPRT = 0). What is
required with this model is to support the new hash page table entry
format an
This helps is following hash only pte bits easily.
We have kept _PAGE_CHG_MASK, _HPAGE_CHG_MASK and _PAGE_PROT_BITS as it
is in this patch eventhough they use hash specific bits. Using them in
radix as it is should be ok, because with radix we expect those bit
positions to be zero.
Only rename in
This patch reduce #ifdef in C code and also help in adding radix changes
later. Only code movement in this patch.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/mm/Makefile | 3 +-
arch/powerpc/mm/init_64.c| 74 ++
arch/powerpc/mm/pgtable-book3e.c | 128 +
I am splitting this as a separate patch to get better review. If ok
we should merge this with previous patch.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/hash.h | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/include/asm/book3s/64
Now that we have moved book3s hash64 linux pte bits to match PowerISA
3.0 radix pte bit position, we move the matching pte bits to common
header.
Only code movement in this patch. No functionality change.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/hash.h| 135 ---
These pte functions will remain the same between radix and hash. Move
them to pgtable.h
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/hash.h| 205 --
arch/powerpc/include/asm/book3s/64/pgtable.h | 209 +++
2 files chang
Radix and hash MMU models support different page table sizes. Make
the #defines a variable so that existing code can work with variable
sizes
Slice related code is only used by hash, so use hash constants there
We will replicate some of the boundary conditions with resepct to
TASK_SIZE using radix
Now that the page table size is a variable, we can move these to
generic pgtable.h
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/hash.h| 15 ---
arch/powerpc/include/asm/book3s/64/pgtable.h | 12
2 files changed, 12 insertions(+), 15 deletion
Only code movement. No functionality change.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/pgtable.h | 142 +--
1 file changed, 71 insertions(+), 71 deletions(-)
diff --git a/arch/powerpc/include/asm/book3s/64/pgtable.h
b/arch/powerpc/include/as
This add PowerISA 3.0 specific pte defines. We share most of the
details with hash linux page table format. This patch indicate only
things where we differ
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/pgtable.h | 1 +
arch/powerpc/include/asm/book3s/64/radix-4k.h |
In this patch we add the radix Kconfig and conditional check.
radix_enabled is written to always return 0 here. Once we have
all needed radix changes added, we will update this to mmu_feature
check.
We need to addt this early so that we can get it all build in the early
stage.
Signed-off-by: Anee
For those pte accessors, that operate on a different set of pte bits
between hash/radix, we add a generic variant that does a conditional
to hash linux or radix variant.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/hash.h| 41 +-
arch/powerpc/include
Here we create pgtable-64/4k.h and move pmd accessors that is common
between hash and radix there. We can't do much sharing with 4k linux
page size [1]. So for now it is empty. In later patches we will add
functions that does conditional hash/radix accessors there.
[1] 4k linux page size with hash
This only does 64k linux page support for now. 64k hash linux config
THP need to differentiate it from hugetlb huge page because with THP
we need to track hash pte slot information with respect to each subpage.
This is not needed with hugetlb hugepage, because we don't do MPSS with
hugetlb.
Radix
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/mmu.h | 20
arch/powerpc/include/asm/mmu.h | 14 +++---
arch/powerpc/mm/hash_utils_64.c | 6 +++---
3 files changed, 30 insertions(+), 10 deletions(-)
diff --git a/arch/powerpc
This add routines for early setup w.r.t radix. We use device tree
property ibm,processor-radix-AP-encodings to find supported page sizes.
If we don't find above we consider 64K and 4K as supported page sizes.
We do map vmemap using 2M page size if we can. Linear mapping is done
such that we use re
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/hash.h| 8
arch/powerpc/include/asm/book3s/64/pgtable.h | 20
arch/powerpc/include/asm/nohash/64/pgtable.h | 7 +++
arch/powerpc/mm/init_64.c| 5 -
arch/powerpc/
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/pgtable.h | 12
arch/powerpc/include/asm/book3s/64/radix.h | 6 ++
arch/powerpc/mm/pgtable-radix.c | 20
3 files changed, 38 insertions(+)
diff --git a/arch/powerpc/includ
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/mmu_context.h | 25 +
arch/powerpc/kernel/swsusp.c | 2 +-
arch/powerpc/mm/mmu_context_nohash.c | 3 ++-
drivers/cpufreq/pmac32-cpufreq.c | 2 +-
drivers/macintosh/via-pmu.c| 4 +
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/mmu_context.h | 4
arch/powerpc/mm/mmu_context_hash64.c | 42 +++---
2 files changed, 38 insertions(+), 8 deletions(-)
diff --git a/arch/powerpc/include/asm/mmu_context.h
b/arch/powerpc/include/asm/
This file now contain both hash and radix specific code. Rename it to
indicate this better.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/mm/Makefile | 7 +++
arch/powerpc/mm/{mmu_context_hash64.c => mmu_context_book3s64.c} | 0
2 files changed, 3
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/tlbflush-hash.h | 28 ++-
arch/powerpc/include/asm/book3s/64/tlbflush.h | 56 ++
arch/powerpc/include/asm/tlbflush.h| 2 +-
arch/powerpc/mm/tlb_hash64.c |
Core kernel don't track the page size of the va range that we are
invalidating. Hence we end up flushing tlb for the entire mm here.
Later patches will improve this.
We also don't flush page walk cache separetly instead use RIC=2 when
flushing tlb, because we do a mmu gather flush after freeing pa
We are going to add asm changes in the follow up patches. Add the
feature bit now so that we can get it all build. We will enable radix
in the last patch using cpu table.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/mmu.h | 3 ++-
arch/powerpc/include/asm/mmu.h
We also use MMU_FTR_RADIX to branch out from code path specific to
hash.
No functionality change.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/kernel/entry_64.S | 7 +--
arch/powerpc/kernel/exceptions-64s.S | 28 +++-
arch/powerpc/kernel/machine_kexec_
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/platforms/pseries/lpar.c| 14 +++---
arch/powerpc/platforms/pseries/lparcfg.c | 3 ++-
2 files changed, 13 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/platforms/pseries/lpar.c
b/arch/powerpc/platforms/pseries/lpar.c
index
Radix don't need slice support. Catch wrong usage of slice feature
with radix enabled
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/mm/slice.c | 16
1 file changed, 16 insertions(+)
diff --git a/arch/powerpc/mm/slice.c b/arch/powerpc/mm/slice.c
index ee21b8699cee..2b27458902
On return from rtas we access the paca variables and we have 64 bit
disabled. This requires us to limit paca in 32 bit range.
Note: we don't set ppc64_rma_size for radix and because of that we endup
with a limit value of 0.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/kernel/paca.c | 5
This is same as the generic code, but then we have to duplicate
because we need to enable enable this along with hash which set
HAVE_ARCH_UNMAPPED_AREA. Hash need special get_unmapped_area handling
because of limitations around base page size. With radix we don't have
such restrictions.
Signed-off
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/mm/hash_utils_64.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c
index 8dfc6ae85d4a..be5d123b3f61 100644
--- a/arch/powerpc/mm/hash_utils_64.c
+++ b/
This patch start to make a book3s variant for pgalloc headers. We have
multiple book3s specific chanages such as
* 4 level page table
* store physical address in higher level table
* use pte_t * for pgtable_t
Having a book3s 64 specific variant helps to keep code simpler and
remove lots of #ifdef
This revert pgalloc related changes w.r.t implementing 4 level page
table for 64k linux page size and storing of physical address in
higher level page table since they are only applicable to book3s 64
variant and we now have a separate copy for book3s 64. This helps to
keep these headers simpler
S
This moves the nohash variant of pgalloc headers to nohash/ directory
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/32/pgalloc.h | 6 +++---
arch/powerpc/include/asm/book3s/64/pgalloc.h | 17 ++--
arch/powerpc/include/asm/book3s/pgalloc.h |
Simplify the code by dropping 4 level page table #ifdef. We are always
4 level now
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/pgalloc.h | 57 +---
1 file changed, 18 insertions(+), 39 deletions(-)
diff --git a/arch/powerpc/include/asm/book3s/6
Only code cleanup. No functionality change.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/pgalloc.h | 12 ++--
arch/powerpc/include/asm/nohash/64/pgalloc.h | 12 ++--
arch/powerpc/mm/pgtable_64.c | 21 -
3 files changed
pgtable_page_dtor for nohash is now moved to pte_fragment_free_mm()
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/pgalloc.h | 147 +++
arch/powerpc/include/asm/nohash/64/pgalloc.h | 38 +--
arch/powerpc/include/asm/page.h | 10 +
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/pgalloc.h | 34
arch/powerpc/include/asm/book3s/64/pgtable.h | 10 ++--
arch/powerpc/mm/hash_utils_64.c | 7 ++
arch/powerpc/mm/pgtable-radix.c | 5 +++-
arch/po
---
arch/powerpc/mm/pgtable.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/powerpc/mm/pgtable.c b/arch/powerpc/mm/pgtable.c
index 115a0a19d5a2..0a9658fbf8b9 100644
--- a/arch/powerpc/mm/pgtable.c
+++ b/arch/powerpc/mm/pgtable.c
@@ -82,6 +82,9 @@ static struct page *maybe_pte_to_page
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/hash.h| 14 +++---
arch/powerpc/include/asm/book3s/64/pgtable.h | 15 ---
arch/powerpc/include/asm/book3s/64/radix.h | 21 +
arch/powerpc/kernel/pci_64.c | 3 ++-
With radix there is no mmu cache. Hence we don't need to do much
in update_mmu_cache.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/mm/mem.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/powerpc/mm/mem.c b/arch/powerpc/mm/mem.c
index f980da6d7569..3164ce720b3e 100644
--- a/arch/p
In this patch we make the number of pte fragments per level4 page table
page a variable. Radix level 4 table size is 256 bytes and hence we
can have 256 fragments per level4 page. We don't update the fragment
count in this patch. We need to do performance measurements to find the
right value for fr
Radix don't use SLICE framework to find page size. Hence use
vma to find the page size.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/mm/hugetlbpage.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/mm/hugetlbpage.c b/arch/powerpc/mm/hugetlbpage.c
inde
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/hugetlb-radix.h | 14
arch/powerpc/include/asm/hugetlb.h | 14
arch/powerpc/mm/Makefile | 1 +
arch/powerpc/mm/hugetlbpage-radix.c| 87 ++
With 4k page size radix config our level 1 page table size 64K and it
should naturally aligned
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/kernel/head_64.S | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/kernel/head_64.S b/arch/powerpc/kernel/h
We have hugepage at the pmd level with 4K radix config. Hence we don't
need to use hugepd format with radix.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/hash-4k.h| 22 +---
arch/powerpc/include/asm/book3s/64/pgtable-4k.h | 46 +
2 fi
THP is only supported by hash64 now and for that we should always
have PTE_ATOMIC_UPDATES always set. Drop the unnecessary #ifdef
in the code.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/mm/pgtable_64.c | 6 +-
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/arch/powerpc/mm
Only code movement in this patch. No functionality change.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/pgtable.h | 24 +-
arch/powerpc/mm/pgtable-hash64.c | 363 ++-
arch/powerpc/mm/pgtable_64.c | 360 ---
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/hash-64k.h| 23 +++-
arch/powerpc/include/asm/book3s/64/pgtable-64k.h | 7 +-
arch/powerpc/include/asm/book3s/64/pgtable.h | 48 +---
arch/powerpc/mm/Makefile | 2 +-
arch/powerpc/mm/p
The deposited pgtable_t is a pte fragment hence we cannot use page->lru
for linking then together. We use the first two 64 bits for pte fragment
as list_head type to link all deposited fragments together. On withdraw
we properly zero then out.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/inc
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/hash-4k.h | 60
arch/powerpc/include/asm/book3s/64/pgtable-64k.h | 60
arch/powerpc/include/asm/book3s/64/pgtable.h | 57 ++
arch/powerpc/platforms/
This patch move the existing p9 hash to a different PVR and add
radix feature with p9 PVR. That implies we will not be able to
runtime select P9 hash. With P9 Radix we need to do
* set UPRT = 0 in cpu setup
* set different TLB set count
We ideally want to use ibm,pa-features to enable disable rad
-page-table-for-book3s-64/20160327-174557
base: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git next
config: x86_64-randconfig-x001-201613 (attached as .config)
reproduce:
# save the attached .config to linux build tree
make ARCH=x86_64
All errors (new ones
-page-table-for-book3s-64/20160327-174557
base: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git next
config: xtensa-allmodconfig (attached as .config)
reproduce:
wget
https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross
-O ~/bin/make.cross
-page-table-for-book3s-64/20160327-174557
base: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git next
config: alpha-allmodconfig (attached as .config)
reproduce:
wget
https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross
-O ~/bin/make.cross
On Sat, Mar 26, 2016 at 11:01:47AM -0700, Sukadev Bhattiprolu wrote:
> From 502e8236082412db1d33abfad95aaf14b539502e Mon Sep 17 00:00:00 2001
> From: Sukadev Bhattiprolu
> Date: Sat, 26 Mar 2016 17:31:39 -0400
> Subject: [PATCH 1/1] perf tools: Fix build break on powerpc
> MIME-Version: 1.0
> Cont
I'll leave it to others to work out whether the general approach & code
in /arch/powerpc is right, but at least for the cxl driver:
Acked-by: Ian Munsie
Excerpts from Aneesh Kumar K.V's message of 2016-03-27 03:23:10 -0500:
> diff --git a/drivers/misc/cxl/fault.c b/drivers/misc/cxl/fault.c
> ind
Excerpts from Aneesh Kumar K.V's message of 2016-03-27 03:23:13 -0500:
> _PAGE_PRIVILEGED means the page can be accessed only by kernel. This is done
> to keep pte bits similar to PowerISA 3.0 radix PTE format. User
> pages are now makred by clearing _PAGE_PRIVILEGED bit.
>
> Previously we allowed
Copying in Andrew Donnellan - this looks to be roughly equivalent to
your patch:
[PATCH] cxl: fix setting of _PAGE_USER bit when handling page faults
I think we were waiting on a v2 of that patch - does the below replace
the need for that?
Also copying cxlflash folk as an FYI
Acked-by: Ian Muns
The Kconfig currently controlling compilation of this code is:
arch/powerpc/platforms/cell/Kconfig:config SPU_BASE
arch/powerpc/platforms/cell/Kconfig:bool
...meaning that it currently is not being built as a module by anyone.
Lets remove the modular code that is essentially orphaned, so tha
The Kconfig for this driver is currently:
config CPU_FREQ_CBE_PMI
bool "CBE frequency scaling using PMI interface"
...meaning that it currently is not being built as a module by
anyone. Lets remove the modular and unused code here, so that
when reading the driver there is no doubt it is buil
My ongoing audit looking for non-modular code that needlessly uses
modular macros (vs. built-in equivalents) and/or has dead code
relating to module unloading that can never be executed led to the
creation of these three powerpc related commits.
One is of the trivial kind, where we substitute in t
The Makefile/Kconfig currently controlling compilation of this code is:
obj-$(CONFIG_PPC64) += setup_64.o sys_ppc32.o \
signal_64.o ptrace32.o \
paca.o nvram_64.o firmware.o
arch/powerpc/platforms/Kconfig.cputype:co
On 27-03-16, 18:08, Paul Gortmaker wrote:
> The Kconfig for this driver is currently:
>
> config CPU_FREQ_CBE_PMI
> bool "CBE frequency scaling using PMI interface"
>
> ...meaning that it currently is not being built as a module by
> anyone. Lets remove the modular and unused code here, so t
* Balbir Singh [2016-03-26 18:11:22]:
> On Fri, Mar 25, 2016 at 3:37 AM, Kamalesh Babulal
> wrote:
> > * Michael Ellerman [2016-03-24 22:04:00]:
> >
> >> Not for merging.
> >>
> >
> > Hi Michael,
> >
> > Loading the livepatch sample module, trigger following warning
> >
>
> The #if IS_MODULE(C
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