Hi Petr,
On Thu, 2016-03-03 at 17:52 +0100, Petr Mladek wrote:
> From: Balbir Singh
>
> Changelog v4:
> 1. Renamed klp_matchaddr() to klp_get_ftrace_location()
> and used it just to convert the function address.
> 2. Synced klp_write_module_reloc() with s390(); made it
>
Hi livepatch maintainers,
On Thu, 2016-03-03 at 17:52 +0100, Petr Mladek wrote:
> From: Balbir Singh
>
> Changelog v4:
> 1. Renamed klp_matchaddr() to klp_get_ftrace_location()
> and used it just to convert the function address.
> 2. Synced klp_write_module_reloc() with s390
On Thu, 2016-03-03 at 11:20 +0100, Peter Zijlstra wrote:
> On Thu, Mar 03, 2016 at 08:23:38PM +1100, Michael Ellerman wrote:
> > On Wed, 2016-03-02 at 12:59 +0100, Peter Zijlstra wrote:
>
> Indeed, but if there's a preemption point in between setting and using
> that state, the ctx->task pointer mi
On 03/03/2016 08:01 AM, Li Zhang wrote:
> --- a/mm/page_alloc.c
> +++ b/mm/page_alloc.c
> @@ -293,13 +293,20 @@ static inline bool update_defer_init(pg_data_t *pgdat,
> unsigned long pfn, unsigned long zone_end,
> unsigned long *nr_initial
On Fri, 4 Mar 2016, Michael Ellerman wrote:
> Obviously it depends heavily on the content of my series, which will go into
> powerpc#next, so it would make sense if this went there too.
>
> I don't see any changes in linux-next for livepatch, so merging it via powerpc
> would probably work fine a
On Fri, 2016-03-04 at 00:57 -0600, Scott Wood wrote:
> This patch fixes a regression that causes any usage of hugetlb
> on e5500 to oops.
>
> The following changes since commit fb822e6076d972691c5dd33431c10f82dda94ae9:
>
> powerpc/hw_breakpoint: Fix oops when destroying hw_breakpoint event
>
Hi,
On Fri, 4 Mar 2016, Michael Ellerman wrote:
> Hi Petr,
>
> On Thu, 2016-03-03 at 17:52 +0100, Petr Mladek wrote:
>
> > From: Balbir Singh
> >
> > Changelog v4:
> > 1. Renamed klp_matchaddr() to klp_get_ftrace_location()
> >and used it just to convert the function address.
> >
For partition running on PHYP, there can be a adjunct partition
which shares the virtual address range with the operating system.
Virtual address ranges which can be used by the adjunct partition
are communicated with virtual device node of the device tree with
a property known as "ibm,reserved-vir
Signed-off-by: Alessio Igor Bogani
---
v2 -> v3
Use appropriate git format-patch flag "-M" to detect renames
v1 -> v2
Address suggestion made by Scott Wood
Split the second patch in two
Don't remove "fsl,mpic" which it is required for 4-cell
interrupt speci
Avoid duplication of the interrupt-parent, migrate to 4 interrupt-cells
and set the right clock-frequency for pcie (100 Mhz).
Signed-off-by: Alessio Igor Bogani
---
arch/powerpc/boot/dts/fsl/gef_ppc9a.dts| 73
arch/powerpc/boot/dts/fsl/gef_sbc310.dts | 79 +
Signed-off-by: Alessio Igor Bogani
---
arch/powerpc/boot/dts/fsl/gef_ppc9a.dts| 258 +++--
arch/powerpc/boot/dts/fsl/gef_sbc310.dts | 246 +++-
arch/powerpc/boot/dts/fsl/gef_sbc610.dts | 258 +++--
arch/powerpc/boot/dts/fsl/mpc86
Scott,
On 3 March 2016 at 21:47, Scott Wood wrote:
> On Wed, 2016-03-02 at 13:16 +0100, Alessio Igor Bogani wrote:
>> Signed-off-by: Alessio Igor Bogani
>> ---
>> v2 -> v3
>> Use appropriate git format-patch flag "-M" to detect renames
>>
>> v1 -> v2
>> Address suggestion made by Scott W
On 03/04/2016 03:20 PM, Anshuman Khandual wrote:
> For partition running on PHYP, there can be a adjunct partition
> which shares the virtual address range with the operating system.
> Virtual address ranges which can be used by the adjunct partition
> are communicated with virtual device node of t
The point of this patch was to break a dependency with cxlflash, so that
they could drop their powerVM changes independently from cxl.
Since this hasn't hit upstream or next yet, change of plan: we've agreed
with cxlflash that the cxl powerVM patchset will do the (small)
modification to cxlf
Move a few functions around to better separate code specific to
bare-metal environment from code which will be commonly used between
guest and bare-metal.
Code specific to bare-metal is meant to be in native.c or pci.c
only. It's basically anything which touches the card p1 registers,
some p2 regi
This series adds support for a cxl card in a powerVM guest.
It requires firmware FW840 and an activation code for cxl (CAPI).
Note that pHyp only claims support for cxlflash, and not generic
support for FPGA CAPI accelerators. cxlflash uses the (slightly
modified) Nallatech card, so the memcopy AF
From: Christophe Lombard
Move around some functions which will be accessed from the bare-metal
and guest environments.
Code in native.c and pci.c is meant to be bare-metal specific.
Other files contain code which may be shared with guests.
Co-authored-by: Frederic Barrat
Signed-off-by: Frederic
CXL kernel API was defining the process problem state area during
context initialization, making it possible to map the problem state
area before attaching the context. This won't work on a powerVM
guest. So force the logical behavior, like in userspace: attach first,
then map the problem state are
The backend API (in cxl.h) lists some low-level functions whose
implementation is different on bare-metal and in a guest. Each
environment implements its own functions, and the common code uses
them through function pointers, defined in cxl_backend_ops
Co-authored-by: Christophe Lombard
Signed-of
Rename a few functions, changing the 'cxl_' prefix to either
'cxl_pci_' or 'cxl_native_', to make clear that the implementation is
bare-metal specific.
Those functions will have an equivalent implementation for a guest in
a later patch.
Co-authored-by: Christophe Lombard
Signed-off-by: Frederic
The PSL interrupt cannot be multiplexed in a guest, as it is not
supported by the hypervisor. So an interrupt will be allocated
for it for each context. It will still be the first interrupt found in
the first interrupt range, but is treated almost like any other AFU
interrupt when creating/deleting
A few functions are mostly common between bare-metal and guest and
just need minor tuning. To avoid crowding the backend API, introduce a
few 'if' based on the CPU being in HV mode.
Co-authored-by: Christophe Lombard
Signed-off-by: Frederic Barrat
Signed-off-by: Christophe Lombard
Reviewed-by:
The context parameter when calling cxl_irq() should be strongly typed.
Co-authored-by: Christophe Lombard
Signed-off-by: Frederic Barrat
Signed-off-by: Christophe Lombard
Reviewed-by: Manoj Kumar
Acked-by: Ian Munsie
---
drivers/misc/cxl/cxl.h | 2 +-
drivers/misc/cxl/irq.c | 3 +--
2 files
From: Christophe Lombard
The hcalls introduced for cxl use a possible new value:
H_STATE (invalid state).
Co-authored-by: Frederic Barrat
Signed-off-by: Frederic Barrat
Signed-off-by: Christophe Lombard
Reviewed-by: Manoj Kumar
Acked-by: Ian Munsie
---
arch/powerpc/include/asm/hvcall.h | 1
From: Christophe Lombard
The hypervisor calls provide an interface with a coherent platform
facility and function. It matches version 0.16 of the 'PAPR changes'
document.
The following hcalls are supported:
H_ATTACH_CA_PROCESSAttach a process element to a coherent platform
From: Christophe Lombard
The new of.c file contains code to parse the device tree to find out
about cxl adapters and AFUs.
guest.c implements the guest-specific callbacks for the backend API.
The process element ID is not known until the context is attached, so
we have to separate the context I
From: Christophe Lombard
The new flash.c file contains the logic to flash a new image on the
adapter, through a hcall. It is an iterative process, with chunks of
data of 1M at a time. There are also 2 phases: write and verify. The
flash operation itself is driven from a user-land tool.
Once flash
From: Christophe Lombard
Filter out a few adapter parameters which don't make sense in a guest.
Document the changes.
Co-authored-by: Frederic Barrat
Signed-off-by: Frederic Barrat
Signed-off-by: Christophe Lombard
Reviewed-by: Manoj Kumar
---
Documentation/ABI/testing/sysfs-class-cxl | 10
Add new entry point to scan the device tree at boot in a guest,
looking for cxl devices.
Co-authored-by: Christophe Lombard
Signed-off-by: Frederic Barrat
Signed-off-by: Christophe Lombard
Reviewed-by: Manoj Kumar
Acked-by: Ian Munsie
---
drivers/misc/cxl/base.c | 25
Like on bare-metal, the cxl driver creates a virtual PHB and a pci
device for the AFU. The configuration space of the device is mapped to
the configuration record of the AFU.
Reuse the code defined in afu_cr_read8|16|32() when reading the
configuration space of the AFU device.
Even though the (vi
From: Christophe Lombard
Check the AFU state whenever an API is called. The hypervisor may
issue a reset of the adapter when it detects a fault. When it happens,
it launches an error recovery which will either move the AFU to a
permanent failure state, or in the disabled state.
If the AFU is foun
From: Christophe Lombard
To ease debugging, add a few tracepoints around the cxl hcalls.
Co-authored-by: Frederic Barrat
Signed-off-by: Frederic Barrat
Signed-off-by: Christophe Lombard
Reviewed-by: Manoj Kumar
Acked-by: Ian Munsie
---
drivers/misc/cxl/hcalls.c | 9 +++
drivers/misc/cxl/
To read the adapter VPD, drivers can't rely on pci config APIs, as it
wouldn't work on powerVM. cxl introduced a new kernel API especially
for this, so start using it.
Co-authored-by: Christophe Lombard
Signed-off-by: Frederic Barrat
Signed-off-by: Christophe Lombard
---
drivers/scsi/cxlflash/
From: Christophe Lombard
Introduce sub-structures containing the bare-metal specific fields in
the structures describing the adapter (struct cxl) and AFU (struct
cxl_afu).
Update all their references.
Co-authored-by: Frederic Barrat
Signed-off-by: Frederic Barrat
Signed-off-by: Christophe Lomb
The cxl_get_phys_dev() API returns a struct device pointer which could
belong to either a struct pci_dev (bare-metal) or platform_device
(powerVM). To avoid potential problems in drivers, remove that API. It
was introduced to allow drivers to read the VPD of the adapter, but
the cxl driver now prov
On Thu, Mar 03, 2016 at 05:52:01PM +0100, Petr Mladek wrote:
[...]
> index ec7f8aada697..2d5333c228f1 100644
> --- a/arch/powerpc/kernel/entry_64.S
> +++ b/arch/powerpc/kernel/entry_64.S
> @@ -1265,6 +1271,31 @@ ftrace_call:
> ld r0, LRSAVE(r1)
> mtlrr0
>
> +#ifdef CONFIG_LIV
On Fri 2016-03-04 13:42:47, Torsten Duwe wrote:
> On Thu, Mar 03, 2016 at 05:52:01PM +0100, Petr Mladek wrote:
> [...]
> > index ec7f8aada697..2d5333c228f1 100644
> > --- a/arch/powerpc/kernel/entry_64.S
> > +++ b/arch/powerpc/kernel/entry_64.S
> > @@ -1265,6 +1271,31 @@ ftrace_call:
> > ld
On Fri, Mar 4, 2016 at 4:48 PM, Vlastimil Babka wrote:
> On 03/03/2016 08:01 AM, Li Zhang wrote:
>> --- a/mm/page_alloc.c
>> +++ b/mm/page_alloc.c
>> @@ -293,13 +293,20 @@ static inline bool update_defer_init(pg_data_t *pgdat,
>> unsigned long pfn, unsigned long zone_
Looks good !
Reviewed-by: Uma Krishnan
On 3/4/2016 5:26 AM, Frederic Barrat wrote:
To read the adapter VPD, drivers can't rely on pci config APIs, as it
wouldn't work on powerVM. cxl introduced a new kernel API especially
for this, so start using it.
Co-authored-by: Christophe Lombard
Signed
This patch should have also been sent to the SCSI list (included now).
Changes look fine.
Acked-by: Matthew R. Ochs
> On Mar 4, 2016, at 5:26 AM, Frederic Barrat
> wrote:
>
> To read the adapter VPD, drivers can't rely on pci config APIs, as it
> wouldn't work on powerVM. cxl introduced a ne
Fred:
Thanks for submitting this. Including linux-scsi.
Acked-by: Manoj N. Kumar
- Manoj
On 3/4/2016 5:26 AM, Frederic Barrat wrote:
To read the adapter VPD, drivers can't rely on pci config APIs, as it
wouldn't work on powerVM. cxl introduced a new kernel API especially
for this, so start
On Thu, 3 Mar 2016, Michael Ellerman wrote:
> On Wed, 2016-03-02 at 12:49 -0800, Hugh Dickins wrote:
> > On Fri, 26 Feb 2016, Hugh Dickins wrote:
> > > On Thu, 25 Feb 2016, Hugh Dickins wrote:
> > > > On Wed, 24 Feb 2016, Hugh Dickins wrote:
> > > > > On Thu, 25 Feb 2016, Aneesh Kumar K.V wrote:
>
On Fri, Mar 04, 2016 at 02:01:37PM +0100, Petr Mladek wrote:
>
> Do I understand it correctly that we could not patch functions that
> pass arguments on the stack with this implementation? If yes, how hard
> would be to get it working, please? At least, it would be great to
> catch this problem an
On Fri, Mar 04, 2016 at 07:16:57PM +0100, Torsten Duwe wrote:
> On Fri, Mar 04, 2016 at 02:01:37PM +0100, Petr Mladek wrote:
> >
> > Do I understand it correctly that we could not patch functions that
> > pass arguments on the stack with this implementation? If yes, how hard
> > would be to get it
The first 5 patches of this series contain fixes to support
the cxlflash driver in a PowerVM guest. For the cxlflash driver
to be functional in a PowerVM guest, a corresponding set of cxl
patches (currently being upstreamed) is required. Note that this
cxlflash patch series does not have any build
From: "Manoj N. Kumar"
The calls to pci_request_regions(), pci_resource_start(),
pci_set_dma_mask(), pci_set_master() and pci_save_state() are all
unnecessary for the IBM CXL flash adapter since data buffers
are not required to be mapped to the device's memory.
The use of services such as pci_se
When operating in the PowerVM environment, the cxlflash module can
receive an error from the hypervisor indicating that there are
existing mappings in the page table for the process MMIO space.
This issue exists because term_afu() currently invokes term_mc()
before stop_afu(), allowing for the mas
From: "Matthew R. Ochs"
Presently, context information structures are allocated and
initialized in the same routine, create_context(). This imposes
an ordering restriction such that all pieces of information needed
to initialize a context must be known before the context is even
allocated.
This
From: "Matthew R. Ochs"
The cxlflash_disk_attach() routine currently uses a cascading error
gate strategy for its error cleanup path. While this strategy is
commonly used to handle cleanup scenarios, it is too restrictive when
function callouts need to be restructured. Problems range from
inserti
From: "Manoj N. Kumar"
When switching to the internal LUN defined on the
IBM CXL flash adapter, there is an unnecessary
scan occurring on the second port. This scan leads
to the following extra lines in the log:
Dec 17 10:09:00 tul83p1 kernel: [ 3708.561134] cxlflash 0008:00:00.0:
cxlflash_queu
In order to support cxlflash in the PowerVM environment, underlying
hypervisor APIs have imposed a kernel API ordering change.
For the superpipe access to LUN, user applications need a context.
The cxlflash module creates this context by making a sequence of
cxl calls. In the current code, a conte
From: "Manoj N. Kumar"
With the current value of cmd_per_lun at 16, the throughput
over a single adapter is limited to around 150kIOPS.
Increase the value of cmd_per_lun to 256 to improve
throughput. With this change a single adapter is able to
attain close to the maximum throughput (380kIOPS).
Hi Petr,
On Thu, Mar 03, 2016 at 05:52:01PM +0100, Petr Mladek wrote:
> From: Balbir Singh
>
> Changelog v4:
> 1. Renamed klp_matchaddr() to klp_get_ftrace_location()
> and used it just to convert the function address.
> 2. Synced klp_write_module_reloc() with s390(); made i
On Tue, Sep 22, 2015 at 04:34:25PM +0200, Christophe Leroy wrote:
> @@ -137,6 +130,45 @@ static inline __wsum csum_add(__wsum csum, __wsum addend)
> #endif
> }
>
> +/*
> + * This is a version of ip_compute_csum() optimized for IP headers,
> + * which always checksum on 4 octet boundaries. ihl
On Tue, Mar 01, 2016 at 03:09:37PM +0800, Zhao Qiang wrote:
> Add IC, SI and SIRAM document of QE to
> Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/qe.txt
>
> Signed-off-by: Zhao Qiang
> ---
> Changes for v2
> - Add interrupt-controller in Required properties
> - delete addres
On Tue, Mar 01, 2016 at 03:09:38PM +0800, Zhao Qiang wrote:
> Add ucc hdlc document to
> Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/network.txt
>
> Signed-off-by: Zhao Qiang
> ---
> Changes for v2
> - use ucc-hdlc instead of ucc_hdlc
> - add more information to properties.
>
On Tue, Mar 01, 2016 at 03:09:39PM +0800, Zhao Qiang wrote:
> Add uqe_serial document to
> Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/uqe_serial.txt
>
> Signed-off-by: Zhao Qiang
> ---
> Changes for v2
> - modify tx/rx-clock-name specification
> Changes for v2
> - NA
>
>
On Tue, Mar 01, 2016 at 03:09:40PM +0800, Zhao Qiang wrote:
> cpm_qe is supported on both powerpc and arm.
> and the QE code has been moved from arch/powerpc into
> drivers/soc/fsl, so move cpm_qe binding from powerpc/fsl
> to soc/fsl
>
> Signed-off-by: Zhao Qiang
> ---
I already acked this. In
On Tue, Sep 22, 2015 at 04:34:36PM +0200, Christophe Leroy wrote:
> +/*
> + * computes the checksum of a memory block at buff, length len,
> + * and adds in "sum" (32-bit)
> + *
> + * returns a 32-bit number suitable for feeding into itself
> + * or csum_tcpudp_magic
> + *
> + * this function must
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