On 2/11/16, Christophe Leroy wrote:
> This patch provides VIRT_CPU_ACCOUTING to PPC32 architecture.
> PPC32 doesn't have the PACA structure, so we use the task_info
> structure to store the accounting data.
>
> In order to reuse on PPC32 the PPC64 functions, all u64 data has
> been replaced by 'un
This is a note to let you know that I've just added the patch titled
sched: Fix crash in sched_init_numa()
to the 4.3-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
sched-fix-crash-in
This is a note to let you know that I've just added the patch titled
sched: Fix crash in sched_init_numa()
to the 4.4-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
sched-fix-crash-in
4.4-stable review patch. If anyone has any objections, please let me know.
--
From: Raghavendra K T
commit 9c03ee147193645be4c186d3688232fa438c57c7 upstream.
The following PowerPC commit:
c118baf80256 ("arch/powerpc/mm/numa.c: do not allocate bootmem memory for non
existin
4.3-stable review patch. If anyone has any objections, please let me know.
--
From: Raghavendra K T
commit 9c03ee147193645be4c186d3688232fa438c57c7 upstream.
The following PowerPC commit:
c118baf80256 ("arch/powerpc/mm/numa.c: do not allocate bootmem memory for non
existin
When eeh_dump_pe_log() is called in eeh_slot_error_detail(), we
already have the check that the PE isn't in PCI config blocked
state. So we needn't the duplicated check in eeh_dump_pe_log().
This removes the duplicated check in eeh_dump_pe_log().
Signed-off-by: Gavin Shan
---
arch/powerpc/kerne
SPAPR_TCE_SHIFT is used in few places only and since IOMMU_PAGE_SHIFT_4K
can be easily used instead, remove SPAPR_TCE_SHIFT.
Signed-off-by: Alexey Kardashevskiy
Reviewed-by: David Gibson
---
arch/powerpc/include/asm/kvm_book3s_64.h | 2 --
arch/powerpc/kvm/book3s_64_vio.c | 3 ++-
arch/
This reworks the existing H_PUT_TCE/H_GET_TCE handlers to have following
patches applied nicer.
This moves the ioba boundaries check to a helper and adds a check for
least bits which have to be zeros.
The patch is pretty mechanical (only check for least ioba bits is added)
so no change in behavio
At the moment only spapr_tce_tables updates are protected against races
but not lookups. This fixes missing protection by using RCU for the list.
As lookups also happen in real mode, this uses
list_for_each_entry_lockless() (which is expected not to access any
vmalloc'd memory).
This converts rele
These patches enable in-kernel acceleration for H_PUT_TCE_INDIRECT and
H_STUFF_TCE hypercalls which allow doing multiple (up to 512) TCE entries
update in a single call saving time on switching context. QEMU already
supports these hypercalls so this is just an optimization.
Both HV and PR KVM mode
This makes vmalloc_to_phys() public as there will be another user
(KVM in-kernel VFIO acceleration) for it soon. As this new user
can be compiled as a module, this exports the symbol.
As a little optimization, this changes the helper to call
vmalloc_to_pfn() instead of vmalloc_to_page() as the siz
At the moment pages used for TCE tables (in addition to pages addressed
by TCEs) are not counted in locked_vm counter so a malicious userspace
tool can call ioctl(KVM_CREATE_SPAPR_TCE) as many times as
RLIMIT_NOFILE and lock a lot of memory.
This adds counting for pages used for TCE tables.
This
This adds real and virtual mode handlers for the H_PUT_TCE_INDIRECT and
H_STUFF_TCE hypercalls for user space emulated devices such as IBMVIO
devices or emulated PCI. These calls allow adding multiple entries
(up to 512) into the TCE table in one call which saves time on
transition between kernel a
Upcoming multi-tce support (H_PUT_TCE_INDIRECT/H_STUFF_TCE hypercalls)
will validate TCE (not to have unexpected bits) and IO address
(to be within the DMA window boundaries).
This introduces helpers to validate TCE and IO address. The helpers are
exported as they compile into vmlinux (to work in
On Tue, 2016-02-09 at 06:50 +0530, Aneesh Kumar K.V wrote:
>
> Also make sure we wait for irq disable section in other cpus to finish
> before flipping a huge pte entry with a regular pmd entry. Code paths
> like find_linux_pte_or_hugepte depend on irq disable to get
> a stable pte_t pointer. A pa
On Mon, Feb 08, 2016 at 02:50:19PM +0530, Aneesh Kumar K.V wrote:
> With next generation power processor, we are having a new mmu model
> [1] that require us to maintain a different linux page table format.
>
> Inorder to support both current and future ppc64 systems with a single
> kernel we need
On 15/02/16 10:52, Gavin Shan wrote:
When eeh_dump_pe_log() is called in eeh_slot_error_detail(), we
already have the check that the PE isn't in PCI config blocked
state. So we needn't the duplicated check in eeh_dump_pe_log().
This removes the duplicated check in eeh_dump_pe_log().
Signed-off-
Balbir Singh writes:
> On Tue, 2016-02-09 at 06:50 +0530, Aneesh Kumar K.V wrote:
>>
>> Also make sure we wait for irq disable section in other cpus to finish
>> before flipping a huge pte entry with a regular pmd entry. Code paths
>> like find_linux_pte_or_hugepte depend on irq disable to get
>
Paul Mackerras writes:
> On Mon, Feb 08, 2016 at 02:50:19PM +0530, Aneesh Kumar K.V wrote:
>> With next generation power processor, we are having a new mmu model
>> [1] that require us to maintain a different linux page table format.
>>
>> Inorder to support both current and future ppc64 systems
On Mon, Feb 08, 2016 at 02:50:20PM +0530, Aneesh Kumar K.V wrote:
> With next generation power processor, we are having a new mmu model
> [1] that require us to maintain a different linux page table format.
>
> Inorder to support both current and future ppc64 systems with a single
> kernel we need
On Mon, Feb 08, 2016 at 02:50:21PM +0530, Aneesh Kumar K.V wrote:
> We move large part of fsl related code to hugetlbpage-book3e.c.
> Only code movement. This also avoid #ifdef in the code.
>
> Signed-off-by: Aneesh Kumar K.V
I am wondering why you are adding #ifdef CONFIG_PPC_FSL_BOOK3E
instanc
Cover-letter for V1 of the series is at
https://lists.ozlabs.org/pipermail/linuxppc-dev/2015-November/136350.html
Cover-letter for V2 of the series is at
https://lists.ozlabs.org/pipermail/linuxppc-dev/2016-January/138054.html
Changes in V3:
Addressed review comments from Michael Neuling
- Made
Loop in assembly checking the registers with many threads.
Signed-off-by: Cyril Bur
---
tools/testing/selftests/powerpc/math/.gitignore| 2 +
tools/testing/selftests/powerpc/math/Makefile | 5 +-
tools/testing/selftests/powerpc/math/fpu_asm.S | 34 +++
tools/testing/selftes
Load up the non volatile FPU and VMX regs and ensure that they are the
expected value in a signal handler
Signed-off-by: Cyril Bur
---
tools/testing/selftests/powerpc/math/.gitignore | 2 +
tools/testing/selftests/powerpc/math/Makefile | 4 +-
tools/testing/selftests/powerpc/math/fpu_s
Test that the non volatile floating point and Altivec registers get
correctly preserved across the fork() syscall.
fork() works nicely for this purpose, the registers should be the same for
both parent and child
Signed-off-by: Cyril Bur
---
tools/testing/selftests/powerpc/Makefile |
Currently when threads get scheduled off they always giveup the FPU,
Altivec (VMX) and Vector (VSX) units if they were using them. When they are
scheduled back on a fault is then taken to enable each facility and load
registers. As a result explicitly disabling FPU/VMX/VSX has not been
necessary.
Currently the FPU, VEC and VSX facilities are lazily loaded. This is not a
problem unless a process is using these facilities.
Modern versions of GCC are very good at automatically vectorising code, new
and modernised workloads make use of floating point and vector facilities,
even the kernel make
This prepares for the decoupling of saving {fpu,altivec,vsx} registers and
marking {fpu,altivec,vsx} as being unused by a thread.
Currently giveup_{fpu,altivec,vsx}() does both however optimisations to
task switching can be made if these two operations are decoupled.
save_all() will permit the sav
This patch adds the ability to be able to save the VEC registers to the
thread struct without giving up (disabling the facility) next time the
process returns to userspace.
This patch builds on a previous optimisation for the FPU registers in the
thread copy path to avoid a possibly pointless relo
This patch adds the ability to be able to save the FPU registers to the
thread struct without giving up (disabling the facility) next time the
process returns to userspace.
This patch optimises the thread copy path (as a result of a fork() or
clone()) so that the parent thread can return to usersp
This patch adds the ability to be able to save the VSX registers to the
thread struct without giving up (disabling the facility) next time the
process returns to userspace.
This patch builds on a previous optimisation for the FPU and VEC registers
in the thread copy path to avoid a possibly pointl
> Now we can't depend for mm_cpumask, a parallel find_linux_pte_hugepte
> can happen outside that. Now i had a variant for kick_all_cpus_sync that
> ignored idle cpus. But then that needs more verification.
>
> http://article.gmane.org/gmane.linux.ports.ppc.embedded/81105
Can be racy as a CPU mov
On Mon, Feb 15, 2016 at 12:55:03PM +1100, Alexey Kardashevskiy wrote:
> This makes vmalloc_to_phys() public as there will be another user
> (KVM in-kernel VFIO acceleration) for it soon. As this new user
> can be compiled as a module, this exports the symbol.
>
> As a little optimization, this cha
On Mon, Feb 15, 2016 at 12:55:06PM +1100, Alexey Kardashevskiy wrote:
> At the moment pages used for TCE tables (in addition to pages addressed
> by TCEs) are not counted in locked_vm counter so a malicious userspace
> tool can call ioctl(KVM_CREATE_SPAPR_TCE) as many times as
> RLIMIT_NOFILE and l
On Mon, Feb 15, 2016 at 12:55:04PM +1100, Alexey Kardashevskiy wrote:
> This reworks the existing H_PUT_TCE/H_GET_TCE handlers to have following
> patches applied nicer.
>
> This moves the ioba boundaries check to a helper and adds a check for
> least bits which have to be zeros.
>
> The patch is
On Mon, Feb 08, 2016 at 02:50:24PM +0530, Aneesh Kumar K.V wrote:
> Also split pgalloc 64k and 4k headers
>
> Signed-off-by: Aneesh Kumar K.V
In the subject: s/defintions/definitions/; s/seperate/separate/
A more detailed patch description would be good. Apart from that,
Reviewed-by: Paul Mac
Paul Mackerras writes:
> On Mon, Feb 08, 2016 at 02:50:17PM +0530, Aneesh Kumar K.V wrote:
>> Signed-off-by: Aneesh Kumar K.V
>
> This needs a proper patch description.
>
> Paul.
I am expecting part1, 2 and 3 will be folded into one patch before
merge. I updated part1 with
powerpc/mm: Copy pga
Add support of suspend, resume function to support deep sleep.
Also make sure of SRAM initialization during resume.
Signed-off-by: Prabhakar Kushwaha
Signed-off-by: Raghav Dogra
---
Changes for v3: Replace spin_event_timeout() with arch independent macro
Based on git://git.kernel.org/pub/scm/l
> -Original Message-
> From: Brian Norris [mailto:computersforpe...@gmail.com]
> Sent: Saturday, February 13, 2016 1:14 AM
> To: Li Yang
> Cc: Raghav Dogra ; linux-...@lists.infradead.org;
> linuxppc-dev ; o...@buserror.net; Prabhakar
> Kushwaha ; Jaiprakash Singh
>
> Subject: Re: [PATC
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