[PATCH] crypto/nx842: Mask XERS0 bit in return value

NX842 coprocessor sets 3rd bit in CR register with XER[S0] which is nothing to do with NX request. Since this bit can be set with other valuable return status, mast this bit. One of other bits (INITIATED, BUSY or REJECTED) will be returned for any given NX request. Signed-off-by: Haren Myneni -

[PATCH] cpufreq: powernv: Redesign the presentation of throttle notification

Replace the throttling event console messages to perf trace event "power:powernv_throttle" and throttle counter stats which are exported in sysfs. The newly added sysfs files are as follows: 1)/sys/devices/system/node/node0/throttle_frequencies This gives the throttle stats for each of the avail

[PATCH] powerpc/476fpe: Add support for kexec

PPC476FPE has a different PVR from previous PPC476 processors. The kexec code checks the PVR in order to correctly setup the MMU. When the initial support for 476FPE processors was added the corresponding change in the kexec code was missed. This patch simply adds the check and solves the following

Re: [PATCH 6/6] cxlflash: Enable device id for future IBM CXL adapter

On 11/12/15 09:54, Uma Krishnan wrote: From: Manoj Kumar This drop enables a future card with a device id of 0x0600 to be recognized by the cxlflash driver. No card specific programming has been added. These card specific changes will be staged in later. Signed-off-by: Manoj N. Kumar Withou

Re: [PATCH 2/6] cxlflash: Fix to avoid virtual LUN failover failure

> Virtual LUNs may be accessed through one or both ports of the adapter. Is it possible that there might ever be adapters with a number of ports other than 2? In particular, is it possible for 3 or 4 port adapters to exist? If so, do you need something with a bit more fidelity? If not, this is

[PATCH V6 0/4] perf/powerpc: Add ability to sample intr machine state in powerpc

This short patch series adds the ability to sample the interrupted machine state for each hardware sample. To test this patchset, Eg: $ perf record -I? # list supported registers output: available registers: gpr0 gpr1 gpr2 gpr3 gpr4 gpr5 gpr6 gpr7 gpr8 gpr9 gpr10 gpr11 gpr12 gpr13 gpr14

[PATCH V6 1/4] perf/powerpc: assign an id to each powerpc register

The enum definition assigns an 'id' to each register in "struct pt_regs" of arch/powerpc. The order of these values in the enum definition are based on the corresponding macros in arch/powerpc/include/uapi/asm/ptrace.h. Signed-off-by: Anju T Reviewed-by : Madhavan Srinivasan --- arch/powerpc/i

[PATCH V6 3/4] tools/perf: Map the ID values with register names

Map ID values with corresponding register names. These names are then displayed when user issues perf record with the -I option followed by perf report/script with -D option. To test this patchset, Eg: $ perf record -I ls # record machine state at interrupt $ perf script -D # read the perf

[PATCH V1 4/4] tool/perf: Add sample_reg_mask to include all perf_regs regs

From: Madhavan Srinivasan Add sample_reg_mask array with pt_regs registers. This is needed for printing supported regs ( -I? option). Signed-off-by: Madhavan Srinivasan --- tools/perf/arch/powerpc/util/Build | 1 + tools/perf/arch/powerpc/util/perf_regs.c | 48 ++

[PATCH V6 2/4] perf/powerpc: add support for sampling intr machine state

The perf infrastructure uses a bit mask to find out valid registers to display. Define a register mask for supported registers defined in asm/perf_regs.h. The bit positions also correspond to register IDs which is used by perf infrastructure to fetch the register values. CONFIG_HAVE_PERF_REGS enabl

Re: [PATCH] cxl: Set endianess of kernel contexts

Acked-by: Ian Munsie ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev