> > > > > For T4240-R1.0-R2.0, the HOSTVER register has incorrcet vender
> > > > > version value and sdhc spec version value. This will break down
> > > > > the ADMA data transfer. So add workaround to get right value
> > > > > VVN=0x13, SVN = 0x1.
> > > >
> > > > So T4240-R1.0-R2.0 is the version
On 08/26/2015 03:11 PM, Alexey Kardashevskiy wrote:
On 08/19/2015 12:01 PM, Wei Yang wrote:
In original design, it tries to group VFs to enable more number of VFs in
the
system, when VF BAR is bigger than 64MB. This design has a flaw in which one
error on a VF will interfere other VFs in the sam
Conditionalize the check using #ifdef
Signed-off-by: Aneesh Kumar K.V
---
mm/kasan/report.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/mm/kasan/report.c b/mm/kasan/report.c
index e07c94fbd0ac..71ce7548d914 100644
--- a/mm/kasan/report.c
+++ b/mm/kasan/report.
We add enable/disable callbacks in this patch which architecture
can implemement. We will use this in the later patches for architecture
like ppc64, that cannot have early zero page kasan shadow region for the
entire virtual address space. Such architectures also cannot use
inline kasan support.
S
Some archs may want to provide kasan shadow memory as a constant
offset from the address. Such arch even though cannot use inline kasan
support, they can work with outofline kasan support.
Signed-off-by: Aneesh Kumar K.V
---
include/linux/kasan.h | 3 +++
mm/kasan/kasan.h | 3 +++
2 files c
This add helper virt_to_pfn and remove the opencoded usage of the
same.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/page.h | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/include/asm/page.h b/arch/powerpc/include/asm/page.h
index 71294a6e976
We can't use generic functions like print_hex_dump to access kasan
shadow region. This require us to setup another kasan shadow region
for the address passed (kasan shadow address). Most architecture won't
be able to do that. Hence remove dumping kasan shadow region dump. If
we really want to do th
Hi,
This patchset implements kernel address sanitizer for ppc64.
Since ppc64 virtual address range is divided into different regions,
we can't have one contigous area for the kasan shadow range. Hence
we don't support the INLINE kasan instrumentation. With Outline
instrumentation, we override the
Now that we have two features KASAN and KASAN_INLINE, add new feature
support file for the same.
Signed-off-by: Aneesh Kumar K.V
---
.../debug/KASAN/KASAN_INLINE/arch-support.txt | 40 ++
.../KASAN/{ => KASAN_OUTLINE}/arch-support.txt | 0
2 files changed, 40 insert
Some of the archs, may find it difficult to support inline KASan
mode. Add HAVE_ARCH_KASAN_INLINE so that we can disable inline
support at config time.
Signed-off-by: Aneesh Kumar K.V
---
arch/x86/Kconfig | 1 +
lib/Kconfig.kasan | 2 ++
scripts/Makefile.kasan | 28 ++---
The function only disable/enable reporting. In the later patch
we will be adding a kasan early enable/disable. Rename kasan_enabled
to properly reflect its function.
Signed-off-by: Aneesh Kumar K.V
---
mm/kasan/kasan.h | 2 +-
mm/kasan/report.c | 2 +-
2 files changed, 2 insertions(+), 2 deleti
We we end up calling kasan_report in real mode, our shadow mapping
for even spinlock variable will show poisoned. This will result
in us calling kasan_report_error with lock_report spin lock held.
To prevent this disable kasan reporting when we are priting
error w.r.t kasan.
Signed-off-by: Aneesh
We use the region with region ID 0xe as the kasan shadow region. Since
we use hash page table, we can't have the early zero page based shadow
region support. Hence we disable kasan in the early code and runtime
enable this. We could imporve the condition using static keys. (but
that is for a later
On 06/24/2015 03:25 PM, Benjamin Herrenschmidt wrote:
Now that the table and the offset can co-exist, we no longer need
to flip/flop, we can just establish both once at boot time.
Signed-off-by: Benjamin Herrenschmidt
---
arch/powerpc/platforms/powernv/pci-ioda.c | 3 +--
arch/powerpc/platf
Missed to cherry-pick the updated version of this patch, before sending
the series out.
commit aeb324e09d95c189eda4ce03790da94b535d1dfc
Author: Aneesh Kumar K.V
Date: Fri Aug 14 12:28:58 2015 +0530
kasan: Don't use kasan shadow pointer in generic functions
We can't use generic fu
On 24.08.15 10:36, Geert Uytterhoeven wrote:
> On Mon, Aug 24, 2015 at 10:34 AM, Geert Uytterhoeven
> wrote:
>> JFYI, when comparing v4.2-rc8[1] to v4.2-rc7[3], the summaries are:
>> - build errors: +4/-7
>
> 4 regressions:
> + /home/kisskb/slave/src/include/linux/kvm_host.h: error: array
>
Mostly uninteresting, though a few worth noting:
CONFIG_BLK_DEV_XIP-> CONFIG_BLK_DEV_RAM_DAX
CONFIG_CLK_PPC_CORENET-> CONFIG_CLK_QORIQ
CONFIG_CRYPTO_ANSI_CPRNG -> was default=m, not anymore
CONFIG_EXT2_FS_XIP-> CONFIG_FS_
Various e500 core have different cache architecture, so they
need different cache flush operations. Therefore, add a callback
function cpu_flush_caches to the struct cpu_spec. The cache flush
operation for the specific kind of e500 is selected at init time.
The callback function will flush all cach
There is a RCPM (Run Control/Power Management) in Freescale QorIQ
series processors. The device performs tasks associated with device
run control and power management.
The driver implements some features: mask/unmask irq, enter/exit low
power states, freeze time base, etc.
Signed-off-by: Chenhui
Freescale CoreNet-based and Non-CoreNet-based platforms require
different PM operations. This patch extracted existing PM operations
on Non-CoreNet-based platforms to a new file which can accommodate
both platforms.
In this way, PM operation codes are clearer structurally.
Signed-off-by: Chenhui Z
Freescale E500MC and E5500 core-based platforms, like P4080, T1040,
support disabling/enabling CPU dynamically.
This patch adds this feature on those platforms.
Signed-off-by: Chenhui Zhao
Signed-off-by: Tang Yuantian
---
major changes for v2:
* factor out smp_85xx_start_cpu()
* move fsl_rcpm_in
Support Freescale E6500 core-based platforms, like t4240.
Support disabling/enabling individual CPU thread dynamically.
Signed-off-by: Chenhui Zhao
---
major changes for v2:
* start Thread1 by Thread0 when we want to boot Thread1 only replacing
the method of changing cpu physical id
arch/powe
On Mon, 2015-24-08 at 12:42:46 UTC, Michael Ellerman wrote:
> From: "Guilherme G. Piccoli"
>
> Commit 1851617cd2da ("PCI/MSI: Disable MSI at enumeration even if kernel
> doesn't support MSI") changed the location of the code that initialises
> dev->msi_cap/msix_cap and then disables MSI/MSI-X int
On Mon, 2015-24-08 at 12:42:47 UTC, Michael Ellerman wrote:
> From: "Guilherme G. Piccoli"
>
> Since commit 1851617cd2da ("PCI/MSI: Disable MSI at enumeration even if
> kernel doesn't support MSI"), the setup of dev->msi_cap/msix_cap and the
> disable of MSI/MSI-X interrupts isn't being done at P
On Mon, 2015-08-17 at 23:30 -0500, Scott Wood wrote:
> Highlights include 32-bit memcpy/memset optimizations, checksum
> optimizations, 85xx config fragments and updates, device tree updates,
> e6500 fixes for non-SMP, and misc cleanup and minor fixes.
>
> The following changes since commit 79cd95
On Wed, 2015-08-26 at 02:49 -0500, Lu Yangbo-B47093 wrote:
> > > > > > For T4240-R1.0-R2.0, the HOSTVER register has incorrcet vender
> > > > > > version value and sdhc spec version value. This will break down
> > > > > > the ADMA data transfer. So add workaround to get right value
> > > > > > VVN=
On Thu, 20 Aug 2015, Michael Ellerman wrote:
> On Wed, 2015-08-19 at 14:39 +, Joseph Myers wrote:
> > I'd like to ping this patch series, not having seen any comments on it.
> >
> > [PATCH 0/8] math-emu: Update kernel math-emu code from current glibc soft-fp
> > https://lkml.org/lkml/2015/7/2
On Wed, Aug 26, 2015 at 4:44 PM, Joseph Myers wrote:
> Ping again for the other-architecture maintainers (alpha, s390, sh,
> sparc)
sh is orphaned, cfr. MAINTAINERS.
Perhaps the J2/J4 people are interested in maintainership?
Gr{oetje,eeting}s,
Geert
--
Geert Uytter
On Wed, 2015-08-26 at 21:47 +1000, Michael Ellerman wrote:
> Mostly uninteresting, though a few worth noting:
>
> CONFIG_BLK_DEV_XIP -> CONFIG_BLK_DEV_RAM_DAX
> CONFIG_CLK_PPC_CORENET -> CONFIG_CLK_QORIQ
> CONFIG_CRYPTO_ANSI_CPRNG-> was default=m, no
2015-08-26 11:26 GMT+03:00 Aneesh Kumar K.V :
> Hi,
>
> This patchset implements kernel address sanitizer for ppc64.
> Since ppc64 virtual address range is divided into different regions,
> we can't have one contigous area for the kasan shadow range. Hence
> we don't support the INLINE kasan instru
2015-08-26 11:26 GMT+03:00 Aneesh Kumar K.V :
> Conditionalize the check using #ifdef
>
> Signed-off-by: Aneesh Kumar K.V
> ---
> mm/kasan/report.c | 11 ---
> 1 file changed, 8 insertions(+), 3 deletions(-)
>
> diff --git a/mm/kasan/report.c b/mm/kasan/report.c
> index e07c94fbd0ac..71ce
2015-08-26 11:26 GMT+03:00 Aneesh Kumar K.V :
> The function only disable/enable reporting. In the later patch
> we will be adding a kasan early enable/disable. Rename kasan_enabled
> to properly reflect its function.
>
> Signed-off-by: Aneesh Kumar K.V
Reviewed-by: Andrey Ryabinin
_
Andrey Ryabinin writes:
> 2015-08-26 11:26 GMT+03:00 Aneesh Kumar K.V :
>> Hi,
>>
>> This patchset implements kernel address sanitizer for ppc64.
>> Since ppc64 virtual address range is divided into different regions,
>> we can't have one contigous area for the kasan shadow range. Hence
>> we don
The previous patch introduced a flag that specified pages in a VMA
should be placed on the unevictable LRU, but they should not be made
present when the area is created. This patch adds the ability to set
this state via the new mlock system calls.
We add MLOCK_ONFAULT for mlock2 and MCL_ONFAULT f
With the refactored mlock code, introduce a new system call for mlock.
The new call will allow the user to specify what lock states are being
added. mlock2 is trivial at the moment, but a follow on patch will add
a new mlock state making it useful.
Signed-off-by: Eric B Munson
Acked-by: Vlastimi
mlock() allows a user to control page out of program memory, but this
comes at the cost of faulting in the entire mapping when it is
allocated. For large mappings where the entire area is not necessary
this is not ideal. Instead of forcing all locked pages to be present
when they are allocated, t
On 08/26/2015 07:44 AM, Joseph Myers wrote:
On Thu, 20 Aug 2015, Michael Ellerman wrote:
On Wed, 2015-08-19 at 14:39 +, Joseph Myers wrote:
I'd like to ping this patch series, not having seen any comments on it.
[PATCH 0/8] math-emu: Update kernel math-emu code from current glibc soft-fp
On Wed, Aug 26, 2015 at 08:09:45PM +0800, Chenhui Zhao wrote:
> +#ifdef CONFIG_PPC_BOOK3E
> +static void qoriq_disable_thread(int cpu)
> +{
> + int hw_cpu = get_hard_smp_processor_id(cpu);
> + int thread = cpu_thread_in_core(hw_cpu);
> +
> + mtspr(SPRN_TENC, TEN_THREAD(thread));
> +}
>
On Wed, Aug 26, 2015 at 08:09:47PM +0800, Chenhui Zhao wrote:
> +int check_cpu_dead(unsigned int cpu)
> +{
> + return per_cpu(cpu_state, cpu) == CPU_DEAD;
> +}
I'm not sure this needs to be a function versus open-coded, but if you do
want to make it a function, make it more obvious from the ca
On Wed, Aug 26, 2015 at 08:09:48PM +0800, Chenhui Zhao wrote:
> + .globl booting_thread_hwid
> +booting_thread_hwid:
> + .long INVALID_THREAD_HWID
> + .align 3
The commit message goes into no detail about the changes you're making to
thread handling, nor are there relevant comments.
On Wed, 2015-08-26 at 18:52 +1000, Alexey Kardashevskiy wrote:
> On 06/24/2015 03:25 PM, Benjamin Herrenschmidt wrote:
> > Now that the table and the offset can co-exist, we no longer need
> > to flip/flop, we can just establish both once at boot time.
> >
> > Signed-off-by: Benjamin Herrenschmidt
On Wed, 2015-08-26 at 09:14 -0500, Scott Wood wrote:
> On Mon, 2015-08-17 at 23:30 -0500, Scott Wood wrote:
> > Highlights include 32-bit memcpy/memset optimizations, checksum
> > optimizations, 85xx config fragments and updates, device tree updates,
> > e6500 fixes for non-SMP, and misc cleanup an
On Wed, 2015-08-26 at 14:44 +, Joseph Myers wrote:
> On Thu, 20 Aug 2015, Michael Ellerman wrote:
>
> > On Wed, 2015-08-19 at 14:39 +, Joseph Myers wrote:
> > > I'd like to ping this patch series, not having seen any comments on it.
> > >
> > > [PATCH 0/8] math-emu: Update kernel math-emu
On Wed, 2015-08-26 at 09:21 -0500, Scott Wood wrote:
> On Wed, 2015-08-26 at 21:47 +1000, Michael Ellerman wrote:
> > Mostly uninteresting, though a few worth noting:
...
> > 91 files changed, 19 insertions(+), 128 deletions(-)
>
> This conflicts with the 85xx config fragment patches that I've al
This applies cleanup on pci_dn_reconfig_notifier(), no functional
changes:
* Rename variable "pci" to "pdn" to indicate its purpose clearly.
* The parent node can be released at any time. So it should be
hold with of_get_parent() before accessing it.
* The device node doesn't have to
Commit cca87d30 ("powerpc/pci: Refactor pci_dn") introduced pdn
list for SRIOV VFs. It means the pdn is be put into the child list
of its parent pdn when the pdn is created. When doing PCI hot
unplugging on pSeries, the PCI device node as well as its pdn are
released through procfs entry "powerpc/o
No need to have two atomic opertions (update and fetch/check) when
decreasing PE's number of passed devices as one atomic operation
is enough.
Signed-off-by: Gavin Shan
---
arch/powerpc/kernel/eeh.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/powerpc/kernel/eeh.c b
"powerpc/iommu: Cleanup setting of DMA base/offset" expects that
the default DMA offset is set from pnv_ioda_setup_bus_dma() which
is correct unless it is SRIOV where the code flow is different - at
the moment when pnv_ioda_setup_bus_dma() is called, there is no PE for
the just created VF.
This ad
Commit 84ad6e5c added LEDS support for PowerNV platform. Lets
update ppc64_defconfig to pick LEDS driver.
PowerNV LEDS driver looks for "/ibm,opal/leds" node in device
tree and loads if this node exists. Hence added it as 'm'.
Also note that powernv LEDS driver needs NEW_LEDS and LEDS_CLASS
as we
On Thu, Aug 27, 2015 at 04:01:16PM +1000, Alexey Kardashevskiy wrote:
>"powerpc/iommu: Cleanup setting of DMA base/offset" expects that
>the default DMA offset is set from pnv_ioda_setup_bus_dma() which
>is correct unless it is SRIOV where the code flow is different - at
>the moment when pnv_ioda_s
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