The encoding of the lengths in the ibm_architecture_vec array is
"interesting" to say the least. It's non-obvious how the number of bytes
we provide relates to the length value.
In fact we already got it wrong once, see 11e9ed43ca8a "Fix up
ibm_architecture_vec definition".
So add some macros to
On Thu, 2014-08-28 at 20:32 +0530, Sudip Mukherjee wrote:
> as pr_* macros are more preffered over printk, so printk replaced with
> corresponding pr_* macros
I suppose ...
> drivers/char/hw_random/pasemi-rng.c | 2 +-
> drivers/char/hw_random/pseries-rng.c | 2 +-
These look OK to me.
che
The problem was reported by Carol: In the scenario of passing mlx4
adapter to guest, EEH error could be recovered successfully. When
returning the device back to host, the driver (mlx4_core.ko)
couldn't be loaded successfully because of error number -5 (-EIO)
returned from mlx4_get_ownership(), whi
>-Original Message-
>From: Wood Scott-B07421
>Sent: Friday, August 29, 2014 12:26 AM
>To: Lu Jingchang-B35083
>Cc: mturque...@linaro.org; linuxppc-dev@lists.ozlabs.org; linux-
>ker...@vger.kernel.org; linux-arm-ker...@lists.infradead.org
>Subject: Re: [RESEND] clk: ppc-corenet: Add Freescal
This enables PAPR defined feature called Dynamic DMA windows (DDW).
Each Partitionable Endpoint (IOMMU group) has a separate DMA window on
a PCI bus where devices are allows to perform DMA. By default there is
1 or 2GB window allocated at the host boot time and these windows are
used when an IOMMU
This checks that the TCE table page size is not bigger that the size of
a page we just pinned and going to put its physical address to the table.
Otherwise the hardware gets unwanted access to physical memory between
the end of the actual page and the end of the aligned up TCE page.
Signed-off-by
At the moment the iommu_table struct has a set_bypass() which enables/
disables DMA bypass on IODA2 PHB. This is exposed to POWERPC IOMMU code
which calls this callback when external IOMMU users such as VFIO are
about to get over a PHB.
Since the set_bypass() is not really an iommu_table function
At the moment pnv_pci_ioda_tce_invalidate() gets the PE pointer via
container_of(tbl). Since we are going to have to add Dynamic DMA windows
and that means having 2 IOMMU tables per PE, this is not going to work.
This implements pnv_pci_ioda(1|2)_tce_invalidate as a pnv_ioda_pe callback.
This add
Modern IBM POWERPC systems support multiple IOMMU tables per PE
so we need a more reliable way (compared to container_of()) to get
a PE pointer from the iommu_table struct pointer used in IOMMU functions.
At the moment IOMMU group data points to an iommu_table struct. This
introduces a spapr_tce_i
This adds a iommu_table_ops struct and puts pointer to it into
the iommu_table struct. This moves tce_build/tce_free/tce_get/tce_flush
callbacks from ppc_md to the new struct where they really belong to.
This adds an extra @ops parameter to iommu_init_table() to make sure
that we do not leave any
Normally a bitmap from the iommu_table is used to track what TCE entry
is in use. Since we are going to use iommu_table without its locks and
do xchg() instead, it becomes essential not to put bits which are not
implied in the direction flag.
Signed-off-by: Alexey Kardashevskiy
---
arch/powerpc/
This adds missing locks in iommu_take_ownership()/
iommu_release_ownership().
This marks all pages busy in iommu_table::it_map in order to catch
errors if there is an attempt to use this table while ownership over it
is taken.
This only clears TCE content if there is no page marked busy in it_map
At the moment writing new TCE value to the IOMMU table fails with EBUSY
if there is a valid entry already. However PAPR specification allows
the guest to write new TCE value without clearing it first.
Another problem this patch is addressing is the use of pool locks for
external IOMMU users such a
The previous patch introduced iommu_table_ops::exchange() callback
which effectively disabled VFIO on pseries. This implements exchange()
for pseries/lpar so VFIO can work in nested guests.
Since exchaange() callback returns an old TCE, it has to call H_GET_TCE
for every TCE being put to the table
There moves locked pages accounting to helpers.
Later they will be reused for Dynamic DMA windows (DDW).
While we are here, update the comment explaining why RLIMIT_MEMLOCK
might be required to be bigger than the guest RAM.
Signed-off-by: Alexey Kardashevskiy
---
drivers/vfio/vfio_iommu_spapr_t
SPAPR defines an interface to create additional DMA windows dynamically.
"Dynamically" means that the window is not allocated before the guest
even started, the guest can request it later. In practice, existing linux
guests check for the capability and if it is there, they create and map
a DMA wind
This makes use of the it_page_size from the iommu_table struct
as page size can differ.
This replaces missing IOMMU_PAGE_SHIFT macro in commented debug code
as recently introduced IOMMU_PAGE_XXX macros do not include
IOMMU_PAGE_SHIFT.
Signed-off-by: Alexey Kardashevskiy
---
drivers/vfio/vfio_io
This defines and implements VFIO IOMMU API which lets the userspace
create and remove DMA windows.
This updates VFIO_IOMMU_SPAPR_TCE_GET_INFO to return the number of
available windows and page mask.
This adds VFIO_IOMMU_SPAPR_TCE_CREATE and VFIO_IOMMU_SPAPR_TCE_REMOVE
to allow the user space to c
On Sat, 2014-07-12 at 13:21 +0200, Alexander Gordeev wrote:
> PowerPC is the only architecture that makes use of hook
> arch_msi_check_device() and does perform some checks to
> figure out if MSI/MSI-X could be enabled for a device.
> However, there are no reasons why those checks could not
> be do
This patchset:
1) provides several MMU TLB handling optimisation on MPC8xx.
2) adds support of 16k pages on MPC8xx.
All changes have been successfully tested on a custom board equipped with MPC885
The two differences with first version of the patch are:
1) I removed the patch number 10, which was
Since coming 469d62be9263b92f2c3329540cbb1c076111f4f3, SPRG2 is used as a
scratch register just like SPRG0 and SPRG1. So Declare it as such and fix
the comment which is not valid anymore since that commit.
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/reg.h |3 ++-
arch/power
SCRATCH0 and SCRATCH1 are only used in Exceptions prologs where no other
exception can happen. There is therefore no need to preserve them accross
TLB handlers, we can use them there as in other exceptions. One of the
advantages is that they do not suffer CPU6 errata unlike M_TW register.
Signed-o
Exception InstructionAccess does not exist on MPC8xx. No need to branch there
from somewhere else.
Handling can be done directly in InstructionTLBError Exception.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 17 +++--
1 files changed, 7 insertions(+), 10
Since commit 2321f33790a6c5b80322d907a92d5739e7521a13, dirty handling is not
handled here anymore. So we fix the comment.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S |8 ++--
1 files changed, 2 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/kernel/head_8
Since commit 2321f33790a6c5b80322d907a92d5739e7521a13, r10 is not used anymore
after FixupDAR. There is therefore no need to set it up with the value of DAR.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S |7 +++
1 files changed, 3 insertions(+), 4 deletions(-)
diff
Branching takes two cycles on MPC8xx. Lets duplicate the two instructions
and avoid the branching.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S |6 --
1 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kerne
r10 and r3 are only used inside FixupDAR function. So lets save them inside
that function only.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 27 +--
1 files changed, 13 insertions(+), 14 deletions(-)
diff --git a/arch/powerpc/kernel/head_8xx.S
This patch activates the handling of 16k pages on the MPC8xx.
Signed-off-by: Christophe Leroy
---
arch/powerpc/Kconfig |2 +-
arch/powerpc/include/asm/mmu-8xx.h |2 ++
arch/powerpc/kernel/head_8xx.S |4
3 files changed, 7 insertions(+), 1 deletions(-)
diff --
When a PMD entry is valid, _PMD_PRESENT is set. Therefore, forcing that bit
during TLB loading is useless.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S |2 --
1 files changed, 0 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/k
By XORing the upper part of the instruction code, we get a value that can
directly be verified with the second test and we can remove the first test.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S |6 ++
1 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/
There is not need to restore r10, r11 and cr registers at this end of ITLBmiss
handler as they are saved again to the same place in ITLBError handler we are
jumping to.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S |8 +---
1 files changed, 5 insertions(+), 3 deleti
No need to re-set this bit at each TLB miss. Let's set it in the PTE.
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/pgtable-ppc32.h | 21 +
arch/powerpc/include/asm/pte-8xx.h |7 +--
arch/powerpc/kernel/head_8xx.S | 10 ++
3
MD_TWC can only be used properly with 4k pages.
So lets calculate level 2 table index by ourselves.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 28
1 files changed, 12 insertions(+), 16 deletions(-)
diff --git a/arch/powerpc/kernel/head_8
In DTLBError handler there is not need to restore r10, r11 and cr registers
after fixing DAR as they are saved again to the same place just after.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/
DataAccess exception is never generated by MPC8xx so do the job directly where
it is used to avoid an unnecessary branching.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 23 ++-
1 files changed, 10 insertions(+), 13 deletions(-)
diff --git a/arch/p
For PAGE size related operations, use PAGE size consts in order to be able to
use different page size in the futur.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 30 ++
1 files changed, 18 insertions(+), 12 deletions(-)
diff --git a/arch/pow
The IP is shared on PPC and ARM, this rename it to qoriq for better
represention, and this also add the CLK_OF_DECLARE support for being
initialized by of_clk_init() on ARM.
Signed-off-by: Jingchang Lu
---
changes in v2:
rename the driver name to ppc-qoriq.c for shared on PPC and ARM.
drivers/
Value 0x00f0 is used to force bits in TLB level 2 entry. This value is linked
to the page size and will vary when we change the page size. Lets define a const
for it in order to have it at only one place.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 19 +---
Use M_TW instead of M_TWB for storing Level 1 table address as M_TWB requires
4k aligned tables, which is only the case with 4k pages.
Consequently, we have to calculate the level 1 table index by ourselves.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 48 +
This patch hiddes that SPR address needed for CPU6 ERRATA handling in the macro.
Then we don't have to worry about this address directly in the code.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 29 -
1 files changed, 16 insertions(+), 13 de
On 29 Aug 2014 02:56, "Michael Ellerman" wrote:
>
> On Thu, 2014-08-28 at 09:27 -0500, Rob Herring wrote:
> > On Thu, Aug 28, 2014 at 3:40 AM, Michael Ellerman
> > wrote:
> > > In commit e6a6928c3ea1 "of/fdt: Convert FDT functions to use libfdt",
> > > the kernel stopped supporting old flat devi
Christophe Leroy wrote on 2014/08/29 11:14:37:
>
> Exception InstructionAccess does not exist on MPC8xx. No need to branch
there from somewhere else.
> Handling can be done directly in InstructionTLBError Exception.
>
> Signed-off-by: Christophe Leroy
>
> ---
> arch/powerpc/kernel/head_8xx.
On Fri, Aug 29, 2014 at 6:13 AM, Grant Likely wrote:
> On 29 Aug 2014 02:56, "Michael Ellerman" wrote:
>>
>> On Thu, 2014-08-28 at 09:27 -0500, Rob Herring wrote:
>> > On Thu, Aug 28, 2014 at 3:40 AM, Michael Ellerman
>> > wrote:
>> > > In commit e6a6928c3ea1 "of/fdt: Convert FDT functions to u
Christophe Leroy wrote on 2014/08/29 11:14:40:
>
> No need to re-set this bit at each TLB miss. Let's set it in the PTE.
>
> Signed-off-by: Christophe Leroy
>
> ---
> arch/powerpc/include/asm/pgtable-ppc32.h | 21 +
> arch/powerpc/include/asm/pte-8xx.h |7 +
Christophe Leroy wrote on 2014/08/29 11:14:37:
>
> SCRATCH0 and SCRATCH1 are only used in Exceptions prologs where no other
> exception can happen. There is therefore no need to preserve them
accross
> TLB handlers, we can use them there as in other exceptions. One of the
> advantages is that th
Christophe Leroy wrote on 2014/08/29 11:13:24:
>
> This patchset:
> 1) provides several MMU TLB handling optimisation on MPC8xx.
> 2) adds support of 16k pages on MPC8xx.
> All changes have been successfully tested on a custom board equipped
with MPC885
>
> The two differences with first versio
On Fri, 2014-08-29 at 11:14 +0200, Christophe Leroy wrote:
> No need to re-set this bit at each TLB miss. Let's set it in the PTE.
>
> Signed-off-by: Christophe Leroy
>
> ---
> arch/powerpc/include/asm/pgtable-ppc32.h | 21 +
> arch/powerpc/include/asm/pte-8xx.h |
On Fri, 2014-08-29 at 16:35 +0800, Jingchang Lu wrote:
> The IP is shared on PPC and ARM, this rename it to qoriq for better
> represention, and this also add the CLK_OF_DECLARE support for being
> initialized by of_clk_init() on ARM.
>
> Signed-off-by: Jingchang Lu
> ---
> changes in v2:
> rena
On Fri, 2014-08-29 at 02:17 -0500, Lu Jingchang-B35083 wrote:
> >-Original Message-
> >From: Wood Scott-B07421
> >Sent: Friday, August 29, 2014 12:26 AM
> >To: Lu Jingchang-B35083
> >Cc: mturque...@linaro.org; linuxppc-dev@lists.ozlabs.org; linux-
> >ker...@vger.kernel.org; linux-arm-ker...
I see that the three syscalls seccomp, getrandom and memfd_create are not wired
because of which we get a warning while compilation.
So I wired them up in this patch. What else needs to be done? I tried the
memfd_test after compiling this kernel, but it is failing. What am I missing for
this to wo
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