Since PowerPC64 ABIv2 doesn't have function descriptor
any more, arch_deref_entry_point(), which returns function
entry point from function descriptor, should be updated.
Signed-off-by: Masami Hiramatsu
Cc: Benjamin Herrenschmidt
Cc: Paul Mackerras
Cc: Anoop Thomas Mathew
Cc: Jiri Kosina
Cc:
On ia64 and ppc64, the function pointer does not point the
entry address of the function, but the address of function
discriptor (which contains the entry address and misc
data.) Since the kprobes passes the function pointer stored
by NOKPROBE_SYMBOL() to kallsyms_lookup_size_offset() for
initalizi
On 07/02/2014 04:00 AM, qiang.z...@freescale.com wrote:
>>> +static irqreturn_t flexcan_err_irq(int irq, void *dev_id) {
>>> + struct net_device *dev = dev_id;
>>> + struct flexcan_priv *priv = netdev_priv(dev);
>>> + struct flexcan_regs __iomem *regs = priv->base;
>>> + u32 reg_ctrl, reg_e
(2014/07/02 15:56), Michael Ellerman wrote:
> On Wed, 2014-07-02 at 15:39 +0900, Masami Hiramatsu wrote:
>> (2014/07/02 13:41), Michael Ellerman wrote:
>>> On Tue, 2014-07-01 at 11:21 +0900, Masami Hiramatsu wrote:
(2014/06/30 20:36), Michael Ellerman wrote:
> On Mon, 2014-06-30 at 12:14 +
(2014/07/02 16:00), Masami Hiramatsu wrote:
> Since PowerPC64 ABIv2 doesn't have function descriptor
> any more, arch_deref_entry_point(), which returns function
> entry point from function descriptor, should be updated.
Please ignore this patch, since it is already fixed by Michael
https://git.k
On 06/24/2014 08:57 AM, Varun Sethi wrote:
> is_power_of_2 requires an unsigned long parameter which would
> lead to truncation of 64 bit values on 32 bit architectures.
>
> __ffs also expects an unsigned long parameter thus won't work
> for 64 bit values on 32 bit architectures.
>
> Signed-off-b
On 07/02/2014 03:04 PM, Marc Kleine-Budde wrote:
> -Original Message-
> From: Marc Kleine-Budde [mailto:m...@pengutronix.de]
> Sent: Wednesday, July 02, 2014 3:04 PM
> To: Zhao Qiang-B45475; linuxppc-dev@lists.ozlabs.org; w...@grandegger.com;
> linux-...@vger.kernel.org; Wood Scott-B07421
>
Thanks Emil.
> -Original Message-
> From: Emil Medve [mailto:emilian.me...@freescale.com]
> Sent: Wednesday, July 02, 2014 1:16 PM
> To: Sethi Varun-B16395; io...@lists.linux-foundation.org;
> j...@8bytes.org; linux-ker...@vger.kernel.org; linuxppc-
> d...@lists.ozlabs.org; alex.william...
On 07/02/2014 10:32 AM, qiang.z...@freescale.com wrote:
> On 07/02/2014 03:04 PM, Marc Kleine-Budde wrote:
>> -Original Message-
>> From: Marc Kleine-Budde [mailto:m...@pengutronix.de]
>> Sent: Wednesday, July 02, 2014 3:04 PM
>> To: Zhao Qiang-B45475; linuxppc-dev@lists.ozlabs.org; w...@gr
Paul Mackerras writes:
> On Sun, Jun 29, 2014 at 04:47:33PM +0530, Aneesh Kumar K.V wrote:
>> We want to use virtual page class key protection mechanism for
>> indicating a MMIO mapped hpte entry or a guest hpte entry that is swapped out
>> in the host. Those hptes will be marked valid, but have
Paul Mackerras writes:
> On Sun, Jun 29, 2014 at 04:47:34PM +0530, Aneesh Kumar K.V wrote:
>> As per ISA, we first need to mark hpte invalid (V=0) before we update
>> the hpte lower half bits. With virtual page class key protection mechanism
>> we want
>> to send any fault other than key fault t
Paul Mackerras writes:
> On Sun, Jun 29, 2014 at 04:47:31PM +0530, Aneesh Kumar K.V wrote:
>> This makes it consistent with h_enter where we clear the key
>> bits. We also want to use virtual page class key protection mechanism
>> for indicating host page fault. For that we will be using key clas
On Thu, Jun 26, 2014 at 11:26:43AM +0800, Zhao Qiang wrote:
> ret is unused when CONFIG_FSL_SOC defined,
> so return ret instead of -ENOMEM when the
> kzalloc fails to avoid it.
Applied, thanks.
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On Tue, Jun 10, 2014 at 03:10:30PM +0200, Alexander Gordeev wrote:
> There are PCI devices that require a particular value written
> to the Multiple Message Enable (MME) register while aligned on
> power of 2 boundary value of actually used MSI vectors 'nvec'
> is a lesser of that MME value:
>
>
On 07/01/14 21:39, Mike Snitzer wrote:
> (btw, Bart Van Assche also has issues with commit e8099177 due to hangs
> during cable pull testing of mpath devices -- Bart: curious to know if
> your cable pull tests pass if you just revert bcccff93).
Sorry but even with bcccff93 reverted after a few ite
On Tue, 2014-07-01 at 20:43 -0500, Scott Wood wrote:
> On Wed, Jun 11, 2014 at 06:10:04PM +0800, Shengzhou Liu wrote:
> > +/* controller at 0x24 */
> > +&pci0 {
> > + compatible = "fsl,t2080-pcie", "fsl,qoriq-pcie";
>
> None of your patches add "fsl,qoriq-pcie" to of_device_ids[] in
> corene
The CoreNet Coherency Fabric is part of the memory subsystem on
some Freescale QorIQ chips. It can report coherency violations (e.g.
due to misusing memory that is mapped noncoherent) as well as
transactions that do not hit any local access window, or which hit a
local access window with an invali
Highlights include MAINTAINERS updates, t4240rdb and t2080qds support,
removal of the long-broken mpc8xx pcmcia driver, and various minor fixes
and updates.
The following changes since commit 68986c9f0f4552c34c248501eb0c690553866d6e:
Revert "offb: Add palette hack for little endian" (2014-06-16
when flexcan is not physically linked, command 'cantest' will
trigger an err_irq, add err_irq handler for it.
Signed-off-by: Zhao Qiang
---
Changes for v2:
- use a space instead of tab
- use flexcan_poll_state instead of print
Changes for v3:
- return IRQ_HANDLED if err is
> -Original Message-
> From: Wood Scott-B07421
> Sent: Thursday, July 03, 2014 5:22 AM
> To: linuxppc-dev@lists.ozlabs.org
> Cc: linux-ker...@vger.kernel.org; Bhushan Bharat-R65777
> Subject: [PATCH v2] memory: Freescale CoreNet Coherency Fabric error reporting
> driver
>
> The CoreNet C
hcall tracepoints add quite a few instructions to our hcall path:
plpar_hcall:
mr r2,r2
mfcrr0
stw r0,8(r1)
b 164 < start
ld r12,0(r2)
std r12,32(r1)
cmpdi r12,0
beq 164 <-
Now that we execute the hcall tracepoint entry and exit code out of
line, we can use the same stack across both functions.
Signed-off-by: Anton Blanchard
---
Index: b/arch/powerpc/platforms/pseries/hvCall.S
===
--- a/arch/powerpc/pl
These three patches are required for correct operation of perf counters on
POWER8 boxes when running KVM guests. There were two bugs; not clearing MMCR2
and writing over the saved value when entering a guest. However the first
obscured the second.
Thanks to who mpe helped diagnose the issue and po
These two registers are already saved in the block above. Aside from
being unnecessary, by the time we get down to the second save location
r8 no longer contains MMCR2, so we are clobbering the saved value with
PMC5.
Signed-off-by: Joel Stanley
---
arch/powerpc/kvm/book3s_hv_interrupts.S | 5 ---
Instead of separate bits for every POWER8 PMU feature, have a single one
for v2.07 of the architecture.
This saves us adding a MMCR2 define for a future patch.
Signed-off-by: Joel Stanley
---
arch/powerpc/include/asm/perf_event_server.h | 3 +--
arch/powerpc/perf/core-book3s.c | 6
On POWER8 when switching to a KVM guest we set bits in MMCR2 to freeze
the PMU counters. Aside from on boot they are then never reset,
resulting in stuck perf counters for any user in the guest or host.
We now set MMCR2 to 0 whenever enabling the PMU, which provides a sane
state for perf to use th
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