On Tue, Jul 1, 2014 at 9:58 AM, Geert Uytterhoeven wrote:
> JFYI, when comparing v3.16-rc3[1] to v3.16-rc2[3], the summaries are:
> - build errors: +5/-63
+ /scratch/kisskb/src/kernel/bounds.c: error: -mcall-aixdesc must be
big endian: => 1:0
+ /scratch/kisskb/src/scripts/mod/devicetable-
when flexcan is not physically linked, command 'cantest' will
trigger an err_irq, add err_irq handler for it.
Signed-off-by: Zhao Qiang
---
Changes for v2:
- use a space instead of tab
- use flexcan_poll_state instead of print
Changes for v3:
- return IRQ_HANDLED if err is
This patch adds kernel side support for software breakpoint.
Design is that, by using an illegal instruction, we trap to hypervisor
via Emulation Assistance interrupt, where we check for the illegal instruction
and accordingly we return to Host or Guest. Patch also adds support for
software breakpo
From: Xuelin Shi
the partial xor result must be kept until the next
tx is generated.
Signed-off-by: Xuelin Shi
---
crypto/async_tx/async_xor.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/crypto/async_tx/async_xor.c b/crypto/async_tx/async_xor.c
index 3c562f5..e1bce26
On Mon, Jun 30, 2014 at 10:53:20PM +0100, Andy Lutomirski wrote:
> The core mm code will provide a default gate area based on
> FIXADDR_USER_START and FIXADDR_USER_END if
> !defined(__HAVE_ARCH_GATE_AREA) && defined(AT_SYSINFO_EHDR).
>
> This default is only useful for ia64. arm64, ppc, s390, sh,
On 07/01/2014 10:03 AM, Zhao Qiang wrote:
> when flexcan is not physically linked, command 'cantest' will
> trigger an err_irq, add err_irq handler for it.
>
> Signed-off-by: Zhao Qiang
> ---
> Changes for v2:
> - use a space instead of tab
> - use flexcan_poll_state instead of print
On Mon, Jun 30 2014 at 6:30am -0400,
Paul Mackerras wrote:
> I have a machine on which 3.15 usually fails to boot, and 3.14 boots
> every time. The machine is a POWER8 2-socket server with 20 cores
> (thus 160 CPUs), 128GB of RAM, and 7 SCSI disks connected via a
> hardware-RAID-capable adapter
On Wed, Jun 11, 2014 at 06:10:04PM +0800, Shengzhou Liu wrote:
> +/* controller at 0x24 */
> +&pci0 {
> + compatible = "fsl,t2080-pcie", "fsl,qoriq-pcie";
None of your patches add "fsl,qoriq-pcie" to of_device_ids[] in
corenet_generic.c, so PCIe will not get probed.
Worse, if I add that s
On 07/01/2014 06:04 PM, Marc Kleine-Budde wrote:
> -Original Message-
> From: Marc Kleine-Budde [mailto:m...@pengutronix.de]
> Sent: Tuesday, July 01, 2014 6:04 PM
> To: Zhao Qiang-B45475; linuxppc-dev@lists.ozlabs.org; w...@grandegger.com;
> linux-...@vger.kernel.org; Wood Scott-B07421
> S
Commit 8d6f7c5a: "powerpc/powernv: Make it possible to skip the IRQHAPPENED
check in power7_nap()" added code that prevents cpus from checking for
pending interrupts just before entering sleep state, which is wrong. These
interrupts are delivered during the soft irq disabled state of the cpu.
A cp
On Sun, Jun 29, 2014 at 04:47:30PM +0530, Aneesh Kumar K.V wrote:
> When calculating the lower bits of AVA field, use the shift
> count based on the base page size. Also add the missing segment
> size and remove stale comment.
>
> Signed-off-by: Aneesh Kumar K.V
Acked-by: Paul Mackerras
___
On Wed, 2014-07-02 at 09:19 +0530, Preeti U Murthy wrote:
> Commit 8d6f7c5a: "powerpc/powernv: Make it possible to skip the IRQHAPPENED
> check in power7_nap()" added code that prevents cpus from checking for
> pending interrupts just before entering sleep state, which is wrong. These
> interrupts
On Sun, Jun 29, 2014 at 04:47:33PM +0530, Aneesh Kumar K.V wrote:
> We want to use virtual page class key protection mechanism for
> indicating a MMIO mapped hpte entry or a guest hpte entry that is swapped out
> in the host. Those hptes will be marked valid, but have virtual page
> class key set t
On Tue, 2014-07-01 at 11:21 +0900, Masami Hiramatsu wrote:
> (2014/06/30 20:36), Michael Ellerman wrote:
> > On Mon, 2014-06-30 at 12:14 +0900, Masami Hiramatsu wrote:
> >> Ping? :)
> >
> > Yeah sorry. I started looking at this and got dragged into another mess.
> >
> > You seem to have duplicate
On Sun, Jun 29, 2014 at 04:47:31PM +0530, Aneesh Kumar K.V wrote:
> This makes it consistent with h_enter where we clear the key
> bits. We also want to use virtual page class key protection mechanism
> for indicating host page fault. For that we will be using key class
> index 30 and 31. So preven
On Sun, Jun 29, 2014 at 04:47:34PM +0530, Aneesh Kumar K.V wrote:
> As per ISA, we first need to mark hpte invalid (V=0) before we update
> the hpte lower half bits. With virtual page class key protection mechanism we
> want
> to send any fault other than key fault to guest directly without
> sear
(2014/07/02 13:41), Michael Ellerman wrote:
> On Tue, 2014-07-01 at 11:21 +0900, Masami Hiramatsu wrote:
>> (2014/06/30 20:36), Michael Ellerman wrote:
>>> On Mon, 2014-06-30 at 12:14 +0900, Masami Hiramatsu wrote:
Ping? :)
>>>
>>> Yeah sorry. I started looking at this and got dragged into ano
On Wed, 2014-07-02 at 15:39 +0900, Masami Hiramatsu wrote:
> (2014/07/02 13:41), Michael Ellerman wrote:
> > On Tue, 2014-07-01 at 11:21 +0900, Masami Hiramatsu wrote:
> >> (2014/06/30 20:36), Michael Ellerman wrote:
> >>> On Mon, 2014-06-30 at 12:14 +0900, Masami Hiramatsu wrote:
> Ping? :)
>
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