On 04/09/2014 10:48 PM, Vasant Hegde wrote:
Firmware update on PowerNV platform takes several minutes. During
this time one CPU is stuck in FW and the kernel complains about "soft
lockups".
Ben,
Sorry for the confusion in subject line.. Its just 1 patch.. not 1/60 .
-Vasant
This patch retu
From: Hongbo Zhang
Hi Vinod Koul,
Please have a look at the v3 patch set.
v2 -> v3 change:
Only add "chan->pm_state = RUNNING" for patch[8/8].
v1 -> v2 change:
The only one change is introducing a new patch[1/7] to remove the unnecessary
macro FSL_DMA_LD_DEBUG, thus the total patches number is
From: Hongbo Zhang
Some codes are calling chan_dbg with FSL_DMA_LD_DEBUG surrounded, it is really
unnecessary to use such a macro because chan_dbg is a wrapper of dev_dbg, we do
have corresponding DEBUG macro to switch on/off dev_dbg, and most of the other
codes are also calling chan_dbg directly
From: Hongbo Zhang
Delete attribute DMA_INTERRUPT because fsldma doesn't support this function,
exception will be thrown if talitos is used to offload xor at the same time.
Signed-off-by: Hongbo Zhang
Signed-off-by: Qiang Liu
---
drivers/dma/fsldma.c | 31 ---
1
From: Hongbo Zhang
Methods of accessing DMA contorller registers are inconsistent, some registers
are accessed by DMA_IN/OUT directly, while others are accessed by functions
get/set_* which are wrappers of DMA_IN/OUT, and even for the BCR register, it
is read by get_bcr but written by DMA_OUT.
Th
From: Hongbo Zhang
There are several places where descriptors are freed using identical code.
This patch puts this code into a function to reduce code duplication.
Signed-off-by: Hongbo Zhang
Signed-off-by: Qiang Liu
---
drivers/dma/fsldma.c | 30 ++
1 file chang
From: Hongbo Zhang
These functions will be modified in the next patch in the series. By moving the
function in a patch separate from the changes, it will make review easier.
Signed-off-by: Hongbo Zhang
Signed-off-by: Qiang Liu
---
drivers/dma/fsldma.c | 188 +-
From: Hongbo Zhang
Fix the potential risk when enable config NET_DMA and ASYNC_TX. Async_tx is
lack of support in current release process of dma descriptor, all descriptors
will be released whatever is acked or no-acked by async_tx, so there is a
potential race condition when dma engine is uesd b
From: Hongbo Zhang
The usage of spin_lock_irqsave() is a stronger locking mechanism than is
required throughout the driver. The minimum locking required should be used
instead. Interrupts will be turned off and context will be saved, it is
unnecessary to use irqsave.
This patch changes all insta
From: Hongbo Zhang
This patch adds suspend resume functions for Freescale DMA driver.
.prepare callback is used to stop further descriptors from being added into the
pending queue, and also issue pending queues into execution if there is any.
.suspend callback makes sure all the pending jobs are
Sorry, forgot the cover letter, plus it here.
From: Hongbo Zhang
Date: Thu, 10 Apr 2014 15:16:31 +0800
Subject: [PATCH v3 0/8] DMA: Freescale: driver cleanups and enhancements
Hi Vinod Koul,
Please have a look at the v3 patch set.
v2 -> v3 change:
Only add "chan->pm_state = RUNNING" for patch
> Subject: [PATCH v4] ASoC: fsl_sai: Add clock controls for SAI
>
> The SAI mainly has the following clocks:
> bus clock
> control and configure registers and to generate synchronous
> interrupts and DMA requests.
>
> mclk1, mclk2, mclk3
> to generate the bit clock when the recei
On Thu, Apr 10, 2014 at 03:39:51PM +0800, Xiubo Li-B47053 wrote:
> > diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c
> > index db9f75e..7cd4af9 100644
> > --- a/sound/soc/fsl/fsl_sai.c
> > +++ b/sound/soc/fsl/fsl_sai.c
> > @@ -401,7 +401,23 @@ static int fsl_sai_startup(struct snd_pc
While testing memory hot-remove, I found following dead lock:
Process #1141 is drmgr, trying to remove some memory, i.e. memory499.
It holds the memory_hotplug_mutex, and blocks when trying to remove file
"online" under dir memory499, in kernfs_drain(), at
wait_event(root->deactivate_wai
On Wednesday 09 April 2014 09:18 PM, Dave Hansen wrote:
> On 04/09/2014 01:20 AM, Peter Zijlstra wrote:
>> This still misses out on Ben's objection that its impossible to get this
>> right at compile time for many kernels, since they can boot and run on
>> many different subarchs.
>
> Completely a
From: hongbo.zh...@freescale.com
> Methods of accessing DMA contorller registers are inconsistent, some registers
^^
> are accessed by DMA_IN/OUT directly, while others are accessed by functions
> get/set_* which are wrappers of DMA_IN/OUT, and even for the BCR regist
On Thu, 2014-04-10 at 02:51 -0400, Mike Qiu wrote:
> Unable to handle kernel paging request for data at address 0x
> Faulting instruction address: 0xc0041d78
> Oops: Kernel access of bad area, sig: 11 [#1]
> ...
> NIP [c0041d78] .sys_pciconfig_iobase+0x68/0x1f0
> LR [c00
On 04/10/2014 04:46 PM, David Laight wrote:
From: hongbo.zh...@freescale.com
Methods of accessing DMA contorller registers are inconsistent, some registers
^^
Thanks.
sorry, that it a typo.
I would wait to see if there are other defects I have to correct, if y
On 10.04.14 05:28, Liu ping fan wrote:
On Mon, Apr 7, 2014 at 4:36 PM, Alexander Graf wrote:
On 07.04.14 09:42, Aneesh Kumar K.V wrote:
Alexander Graf writes:
On 03.04.14 04:36, Liu ping fan wrote:
Hi Alex, could you help to pick up this patch? since v3.14 kernel can
enable numa fault fo
On 04/10/2014 03:54 PM, Benjamin Herrenschmidt wrote:
On Thu, 2014-04-10 at 02:51 -0400, Mike Qiu wrote:
Unable to handle kernel paging request for data at address 0x
Faulting instruction address: 0xc0041d78
Oops: Kernel access of bad area, sig: 11 [#1]
...
NIP [c0041d78]
The SAI mainly has the following clocks:
bus clock
control and configure registers and to generate synchronous
interrupts and DMA requests.
mclk1, mclk2, mclk3
to generate the bit clock when the receiver or transmitter is
configured for an internally generated bit clock.
So th
On Thu, 2014-04-10 at 15:10 +0800, hongbo.zh...@freescale.com wrote:
> From: Hongbo Zhang
>
> There are several places where descriptors are freed using identical code.
> This patch puts this code into a function to reduce code duplication.
>
> Signed-off-by: Hongbo Zhang
> Signed-off-by: Qiang
On Thu, 2014-04-10 at 15:10 +0800, hongbo.zh...@freescale.com wrote:
> From: Hongbo Zhang
>
> Fix the potential risk when enable config NET_DMA and ASYNC_TX. Async_tx is
> lack of support in current release process of dma descriptor, all descriptors
> will be released whatever is acked or no-acke
On Thu, 2014-04-10 at 15:10 +0800, hongbo.zh...@freescale.com wrote:
> From: Hongbo Zhang
>
> This patch adds suspend resume functions for Freescale DMA driver.
> .prepare callback is used to stop further descriptors from being added into
> the
> pending queue, and also issue pending queues into
Numerical values stored in the device tree are encoded in Big Endian and
should be byte swapped when running in Little Endian.
RPA hot plug module should convert those values as well.
Note that in rpaphp_get_drc_props the comparison between indexes[i+1] and
*index is done using the BE values (wha
On Thu, Apr 10, 2014 at 07:23:12PM +0800, Nicolin Chen wrote:
> The SAI mainly has the following clocks:
> bus clock
> control and configure registers and to generate synchronous
> interrupts and DMA requests.
>
> mclk1, mclk2, mclk3
> to generate the bit clock when the receiver or
On Thu, Apr 10, 2014 at 10:07:47PM +0800, Shawn Guo wrote:
> On Thu, Apr 10, 2014 at 07:23:12PM +0800, Nicolin Chen wrote:
> > The SAI mainly has the following clocks:
> > bus clock
> > control and configure registers and to generate synchronous
> > interrupts and DMA requests.
> >
> >
On Tue, Apr 8, 2014 at 7:44 PM, Scott Wood wrote:
> On Tue, 2014-03-25 at 14:41 +0100, Valentin Longchamp wrote:
>> These are the bindings for 2 MFD devices used on some of the Keymile boards.
>> The first one is the chassis managmenet bfticu FPGA.
>> The second one is the board controller (reset,
The SAI mainly has the following clocks:
bus clock
control and configure registers and to generate synchronous
interrupts and DMA requests.
mclk1, mclk2, mclk3
to generate the bit clock when the receiver or transmitter is
configured for an internally generated bit clock.
So th
The SAI mainly has the following clocks:
bus clock
control and configure registers and to generate synchronous
interrupts and DMA requests.
mclk1, mclk2, mclk3
to generate the bit clock when the receiver or transmitter is
configured for an internally generated bit clock.
So th
On Thu, Apr 10, 2014 at 12:51 AM, Mike Qiu wrote:
> Unable to handle kernel paging request for data at address 0x
> Faulting instruction address: 0xc0041d78
> Oops: Kernel access of bad area, sig: 11 [#1]
> ...
> NIP [c0041d78] .sys_pciconfig_iobase+0x68/0x1f0
> LR [c00
On Sun, Mar 30, 2014 at 7:14 AM, Alexander Shiyan wrote:
> This patch converts GE I/O FPGA GPIO driver to platform driver.
>
> Signed-off-by: Alexander Shiyan
> ---
> Only compile tested.
Isn't it necessary to also patch affected platforms to add this
device either as platform device or in thei
Thu, 10 Apr 2014 18:30:16 +0200 от Linus Walleij :
> On Sun, Mar 30, 2014 at 7:14 AM, Alexander Shiyan wrote:
>
> > This patch converts GE I/O FPGA GPIO driver to platform driver.
> >
> > Signed-off-by: Alexander Shiyan
> > ---
> > Only compile tested.
>
> Isn't it necessary to also patch affec
On Thu, 2014-04-10 at 09:27 -0600, Bjorn Helgaas wrote:
> Ben, I'll pick this up for v3.15 since the original change
> (3bc955987fb3) went through my tree, unless you want to handle it.
Nah, go for it, I'm about to go on vacation for a week :-)
Thanks !
Cheers,
Ben.
___
In KVM guests on Power, in a guest not backed by hugepages, we see the
following:
AnonHugePages: 0 kB
HugePages_Total: 0
HugePages_Free:0
HugePages_Rsvd:0
HugePages_Surp:0
Hugepagesize: 64 kB
HPAGE_SHIFT == 0 in this configuration, which indicates tha
On Thu, Apr 10, 2014 at 11:26:15PM +0800, Nicolin Chen wrote:
> The SAI mainly has the following clocks:
> bus clock
> control and configure registers and to generate synchronous
> interrupts and DMA requests.
Applied, thanks.
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Description: Digital signature
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Commit 8f619b5429d9 ("powerpc/ppc64: Do not turn AIL (reloc-on
interrupts) too early") added code to set the AIL bit in the LPCR
without checking whether the kernel is running in hypervisor mode.
The result is that when the kernel is running as a guest (i.e.,
under PowerKVM or PowerVM), the process
Benjamin Herrenschmidt wrote:
> Turn them on at the same time as we allow MSR_IR/DR in the paca
> kernel MSR, ie, after the MMU has been setup enough to be able
> to handle relocated access to the linear mapping.
>
> Signed-off-by: Benjamin Herrenschmidt
> ---
> arch/powerpc/kernel/cpu_setup_p
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