Hi Gavin,
On Fri, 28 Jun 2013 13:42:23 +0800 Gavin Shan wrote:
>
> Update MAINTAINERS to reflect recent changes.
>
> Signed-off-by: Gavin Shan
> ---
> MAINTAINERS |6 ++
> 1 files changed, 6 insertions(+), 0 deletions(-)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 5be702c..78e6
On 06/27/2013 10:54 PM, Rob Herring wrote:
>> Rob,
>> Are you ok with phys_addr_t since your concern was about rest
>> of the memory specific bits of the device-tree code use u64 ?
>
> No. I still think it should be u64 for same reasons I said originally.
The physical address space is represente
On Fri, Jun 28, 2013 at 05:46:34PM +1000, Stephen Rothwell wrote:
>Hi Gavin,
>
>On Fri, 28 Jun 2013 13:42:23 +0800 Gavin Shan
>wrote:
>>
>> Update MAINTAINERS to reflect recent changes.
>>
>> Signed-off-by: Gavin Shan
>> ---
>> MAINTAINERS |6 ++
>> 1 files changed, 6 insertions(+), 0
A mistake we have made in the past is that we pull out the fields we
need from the event code, but don't check that there are no unknown bits
set. This means that we can't ever assign meaning to those unknown bits
in future.
Although we have once again failed to do this at release, it is still
ear
In pmu_disable() we disable the PMU by setting the FC (Freeze Counters)
bit in MMCR0. In order to do this we have to read/modify/write MMCR0.
It's possible that we read a value from MMCR0 which has PMAO (PMU Alert
Occurred) set. When we write that value back it will cause an interrupt
to occur. We
On Power8 we can freeze PMC5 and 6 if we're not using them. Normally they
run all the time.
As noticed by Anshuman, we should unfreeze them when we disable the PMU
as there are legacy tools which expect them to run all the time.
Signed-off-by: Michael Ellerman
---
arch/powerpc/include/asm/reg.h
In power_pmu_enable() we can use the existing out label to reduce the
number of return paths.
Signed-off-by: Michael Ellerman
---
arch/powerpc/perf/core-book3s.c |9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/co
In power_pmu_enable() we still enable the PMU even if we have zero
events. This should have no effect but doesn't make much sense. Instead
just return after telling the hypervisor that we are not using the PMCs.
Signed-off-by: Michael Ellerman
---
arch/powerpc/perf/core-book3s.c |7 +--
In commit 59affcd "Context switch more PMU related SPRs" I added more
PMU SPRs to thread_struct, later modified in commit b11ae95. To add
insult to injury it turns out we don't need to switch MMCRA as it's
only user readable, and the value is recomputed by the PMU code.
Signed-off-by: Michael Elle
Add support for EBB (Event Based Branches) on 64-bit book3s. See the
included documentation for more details.
EBBs are a feature which allows the hardware to branch directly to a
specified user space address when a PMU event overflows. This can be
used by programs for self-monitoring with no kerne
Add logic to the power8 PMU code to support EBB. Future processors would
also be expected to implement similar constraints. At that time we could
possibly factor these out into common code.
Finally mark the power8 PMU as supporting EBB, which is the actual
enable switch which allows EBBs to be con
On LPAR systems we need to inform the hypervisor that we are using the
EBB registers. We do this by setting a bit in the Virtual Processor Area
(VPA) - formerly known as the lppaca.
For now we do this always, ie. we do not dynamically enable/disable.
Signed-off-by: Michael Ellerman
---
arch/pow
Thank for Sukadev Bhattip and Xiao Guangrong's help.
Thank for Michael Ellerman's review.
ChangeLog: v2 -> v3:
1. Adding a leading zero to all the events code in "power7-events-list.h"
which don't have a PMC, so that they all line up vertically.
ChangeLog: v1 -> v2:
1. As Michael Ellerman
Power7 supports over 530 different perf events but only a small
subset of these can be specified by name, for the remaining
events, we must specify them by their raw code:
perf stat -e r2003c
This patch makes all the POWER7 events available in sysfs.
So we can instead specify these as:
When we treclaim and trecheckpoint there's an unavoidable period when r1
will not be a valid kernel stack pointer.
This patch clears the MSR recoverable interrupt (RI) bit over these
regions to indicate we have an invalid kernel stack pointer.
For treclaim, the region over which we clear MSR RI i
In the Power7 PMU guide:
https://www.power.org/documentation/commonly-used-metrics-for-performance-analysis/
PM_BRU_MPRED is referred to as PM_BR_MPRED.
It fixed the typo by changing the name of the event in kernel
and documentation accordingly.
This patch changes the ABI, there are some reasons
From: "Aneesh Kumar K.V"
We want to use CMA for allocating hash page table and real mode area for
PPC64. Hence move DMA contiguous related changes into a seperate config
so that ppc64 can enable CMA without requiring DMA contiguous.
Signed-off-by: Aneesh Kumar K.V
---
arch/arm/configs/omap2plu
From: "Aneesh Kumar K.V"
Use CMA for allocation of guest hash page.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/kvm_book3s_64.h | 1 -
arch/powerpc/include/asm/kvm_host.h | 2 +-
arch/powerpc/include/asm/kvm_ppc.h | 8 +-
arch/powerpc/kernel/setup_64.c
From: "Aneesh Kumar K.V"
Use CMA for allocation of RMA region for guest. Also remove linear allocator
now that it is not used
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/kvm_book3s_64.h | 1 +
arch/powerpc/include/asm/kvm_host.h | 12 +--
arch/powerpc/include/asm/kvm_p
From: "Aneesh Kumar K.V"
Both RMA and hash page table request will be a multiple of 256K. We can use
a chunk size of 256K to track the free/used 256K chunk in the bitmap. This
should help to reduce the bitmap size.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/kvm/book3s_hv_cma.c | 35 +
lwepx faults needs to be handled by KVM and this implies additional code
in DO_KVM macro to identify the source of the exception originated from
host context. This requires to check the Exception Syndrome Register
(ESR[EPID]) and External PID Load Context Register (EPLC[EGS]) for DTB_MISS,
DSI and
lwepx faults needs to be handled by KVM. With the current solution
the host kernel searches for the faulting address using its LPID context.
If a host translation is found we return to the lwepx instr instead of the
fixup ending up in an infinite loop.
Revert the commit 1d628af7 "add load inst fix
On Thu, Jun 27, 2013 at 9:54 PM, Rob Herring wrote:
> On 06/21/2013 12:20 PM, Santosh Shilimkar wrote:
>> On Friday 21 June 2013 05:04 AM, Sebastian Andrzej Siewior wrote:
>>> On 06/21/2013 02:52 AM, Santosh Shilimkar wrote:
diff --git a/arch/microblaze/kernel/prom.c b/arch/microblaze/kernel/
The issue was introduced by commit 37f02195 ("powerpc/pci: fix
PCI-e devices rescan issue on powerpc platform"). The field
(struct pci_dev::irq) is reused by PCI core to trace the base
MSI interrupt number if the MSI stuff is enabled on the corresponding
device. When running to pcibios_setup_device
Update MAINTAINERS to reflect recent changes.
Signed-off-by: Gavin Shan
---
MAINTAINERS |8 +++-
1 files changed, 7 insertions(+), 1 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 5be702c..ebeceeb 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3103,6 +3103,13 @@ M: Maxi
Hi
Could you help to confirm:
Kexec-tools 2.0.4 + Linux 2.6.33 on MPC8541(PPC32) can work or not?
If not, how to make it? Thanks a lot.
-Original Message-
From: ext Simon Horman [mailto:ho...@verge.net.au]
Sent: Friday, June 28, 2013 4:17 PM
To: Xia, Zhao (NSN - CN/Shanghai)
Subject: Re
Hi,
On 27 June 2013 21:11, Benjamin Herrenschmidt wrote:
> On Fri, 2013-06-28 at 09:59 +0800, Gavin Shan wrote:
>> Update MAINTAINERS to reflect recent changes.
>>
>> Signed-off-by: Gavin Shan
>> ---
>> MAINTAINERS |4
>> 1 files changed, 4 insertions(+), 0 deletions(-)
>>
>> diff --gi
On Fri, 2013-06-28 at 13:08 +0530, Varun Sethi wrote:
> Following is a brief description of the PAMU hardware:
> PAMU determines what action to take and whether to authorize the action on
> the basis of the memory address, a Logical IO Device Number (LIODN), and
> PAACT table (logically) indexed by
The following set of patches modifies kernel RapidIO subsystem to enable build
and use of its components as loadable kernel modules. Combinations of statically
linked and modular components are also supported.
For this release full RapidIO subsystem modularization is implemented for
x86-based plat
This patch adds an option to build device driver for Tsi721 PCIe-to-SRIO bridge
device as a kernel module.
Currently this module cannot be unloaded because the existing RapidIO subsystem
code does not support dynamic removal of local RapidIO controllers (TODO).
Signed-off-by: Alexandre Bounine
C
Add a configuration option to build RapidIO subsystem core code as a loadable
kernel module. Currently this option is available only for x86-based platforms,
with the additional patch for PowerPC planned to be provided later.
This patch replaces kernel command line parameter "riohdid=" with its
mo
Add RapidIO-specific modalias generation to enable udev notifications about
RapidIO-specific events.
The RapidIO modalias string format is shown below:
"rapidio:vdavad"
Where:
v - Device Vendor ID (16 bit),
d - Device ID (16 bit),
av - Assembly Vendor ID (16 bit),
ad - Assembly
Update enumeration/discovery method registration mechanism to allow loading
enumeration/discovery methods before all mports are registered.
Existing statically linked RapidIO subsystem expects that all available RapidIO
mport devices are initialized and registered before the enumeration/discovery
Update RapidIO documentation files to reflect modularization changes.
Signed-off-by: Alexandre Bounine
Cc: Matt Porter
Cc: Li Yang
Cc: Kumar Gala
Cc: Andre van Herk
Cc: Micha Nelissen
Cc: Stef van Os
Cc: Jean Delvare
---
Documentation/rapidio/rapidio.txt | 98 +++
Rework probe/remove routines to prevent rionet driver from monopolizing
target RapidIO devices. Fix conflict with modular RapidIO switch drivers.
Using one of RapidIO messaging channels rionet driver provides a service layer
common to all endpoint devices in a system's RapidIO network. These devic
Rework RapidIO switch drivers to add an option to build them as loadable
kernel modules.
This patch removes RapidIO-specific vmlinux section and converts switch drivers
to be compatible with LDM driver registration method. To simplify registration
of device-specific callback routines this patch i
On Thu, Mar 07, 2013 at 04:57:45PM +0530, Sandeep Singh wrote:
> +tdm@16000 {
> + compatible = "fsl,tdm1.0";
> + reg = <0x16000 0x200 0x2c000 0x2000>;
> + clock-frequency = <0>;
> + tdm_tx_clk = <2048000>;
> + interrupts = <62 8 0 0>;
> + fsl,max-time-slots = <128>;
> +};
t
On 10:59 Fri 28 Jun , Grant Likely wrote:
> On Thu, Jun 27, 2013 at 9:54 PM, Rob Herring wrote:
> > On 06/21/2013 12:20 PM, Santosh Shilimkar wrote:
> >> On Friday 21 June 2013 05:04 AM, Sebastian Andrzej Siewior wrote:
> >>> On 06/21/2013 02:52 AM, Santosh Shilimkar wrote:
> diff --git a
Sebastian,
On Friday 28 June 2013 09:49 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 10:59 Fri 28 Jun , Grant Likely wrote:
>> On Thu, Jun 27, 2013 at 9:54 PM, Rob Herring wrote:
>>> On 06/21/2013 12:20 PM, Santosh Shilimkar wrote:
On Friday 21 June 2013 05:04 AM, Sebastian Andrzej
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