Hi Linus !
Please pull this regression fix into 3.10. We accidentally broke
hugetlbfs on Freescale embedded processors which use a slightly
different page table layout than our server processors.
Cheers,
Ben.
The following changes since commit c0691143dfe1d42ec9bd89de5921ccb6a27ea1b3:
mn10300
On Thu, 2013-06-20 at 15:28 +1000, David Gibson wrote:
> > Just out of curiosity - would not get_file() and fput_atomic() on a
> group's
> > file* do the right job instead of vfio_group_add_external_user() and
> > vfio_group_del_external_user()?
>
> I was thinking that too. Grabbing a file refere
This patchset is used to support kexec and kdump on book3e.
Tested on fsl-p5040 DS.
v2:
* rebase on merge branch as Ben mention now.
v1:
* improve some patch head
* rebase on next branch with patch 7
Tiejun Chen (7
book3e is different with book3s since 3s includes the exception
vectors code in head_64.S as it relies on absolute addressing
which is only possible within this compilation unit. So we have
to get that label address with got.
And when boot a relocated kernel, we should reset ipvr properly again
af
We need to active KEXEC for book3e and bypass or convert non-book3e stuff
in kexec coverage.
Signed-off-by: Tiejun Chen
---
arch/powerpc/Kconfig |2 +-
arch/powerpc/kernel/machine_kexec_64.c |6 ++
arch/powerpc/kernel/misc_64.S |6 ++
3 files change
book3e have no real MMU mode so we have to create a 1:1 TLB
mapping to make sure we can access the real physical address.
And correct something to support this pseudo real mode on book3e.
Signed-off-by: Tiejun Chen
---
arch/powerpc/kernel/head_64.S |9 ---
arch/powerpc/kernel/misc_64.S |
We need to introduce a flag to indicate we're already running
a kexec kernel then we can go proper path. For example, We
shouldn't access spin_table from the bootloader to up any secondary
cpu for kexec kernel, and kexec kernel already know how to jump to
generic_secondary_smp_init.
Signed-off-by:
ppc64 kexec mechanism has a different implementation with ppc32.
Signed-off-by: Tiejun Chen
---
arch/powerpc/platforms/85xx/smp.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/powerpc/platforms/85xx/smp.c
b/arch/powerpc/platforms/85xx/smp.c
index b308373..18a5f8a 100
Book3e is always aligned 1GB to create TLB so we should
use (KERNELBASE - MEMORY_START) as VIRT_PHYS_OFFSET to
get __pa/__va properly while boot kdump.
Signed-off-by: Tiejun Chen
---
arch/powerpc/include/asm/page.h |2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/powerpc/include/asm
In commit 96f013f, "powerpc/kexec: Add kexec "hold" support for Book3e
processors", requires that GPR4 survive the "hold" process, for IBM Blue
Gene/Q with with some very strange firmware. But for FSL Book3E, r4 = 1
to indicate that the initial TLB entry for this core already exists so
we still sho
On 06/20/2013 05:47 PM, Benjamin Herrenschmidt wrote:
> On Thu, 2013-06-20 at 15:28 +1000, David Gibson wrote:
>>> Just out of curiosity - would not get_file() and fput_atomic() on a
>> group's
>>> file* do the right job instead of vfio_group_add_external_user() and
>>> vfio_group_del_external_user
From: "Aneesh Kumar K.V"
We now have pmd entries covering 16MB range and the PMD table double its
original size.
We use the second half of the PMD table to deposit the pgtable (PTE page).
The depoisted PTE page is further used to track the HPTE information. The
information
include [ secondary g
Hi,
This is the second patchset needed to support THP on ppc64.
mm/ changes are already merged to Andrew's -mm tree.
mm/THP: deposit the transpare huge pgtable before set_pmd
mm/THP: Don't use HPAGE_SHIFT in transparent hugepage code
mm/THP: withdraw the pgtable after pmdp related operations
From: "Aneesh Kumar K.V"
If a hash bucket gets full, we "evict" a more/less random entry from it.
When we do that we don't invalidate the TLB (hpte_remove) because we assume
the old translation is still technically "valid". This implies that when
we are invalidating or updating pte, even if HPTE
From: "Aneesh Kumar K.V"
THP code does PTE page allocation along with large page request and deposit them
for later use. This is to ensure that we won't have any failures when we split
hugepages to regular pages.
On powerpc we want to use the deposited PTE page for storing hash pte slot and
seco
From: "Aneesh Kumar K.V"
Replace find_linux_pte with find_linux_pte_or_hugepte and explicitly
document why we don't need to handle transparent hugepages at callsites.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/pgtable-ppc64.h | 24
arch/powerpc/kernel
From: "Aneesh Kumar K.V"
Reviewed-by: David Gibson
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/mm/hugetlbpage.c | 32 ++--
1 file changed, 26 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/mm/hugetlbpage.c b/arch/powerpc/mm/hugetlbpage.c
index 2865077
From: "Aneesh Kumar K.V"
We will use this in the later patch for handling THP pages
Reviewed-by: David Gibson
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/hugetlb.h | 8 +-
arch/powerpc/include/asm/pgtable-ppc64.h | 13 --
arch/powerpc/include/asm/pgtable.h |
From: "Aneesh Kumar K.V"
We can find pte that are splitting while walking page tables. Return
None pte in that case.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/kvm_book3s_64.h | 58 +++-
arch/powerpc/kvm/book3s_64_mmu_hv.c | 8 +++--
arch/pow
From: "Aneesh Kumar K.V"
Reviewed-by: David Gibson
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/mm/gup.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/mm/gup.c b/arch/powerpc/mm/gup.c
index 4b921af..223a255 100644
--- a/arch/powerpc/mm/gup.c
++
From: "Aneesh Kumar K.V"
The deposted PTE page in the second half of the PMD table is used to
track the state on hash PTEs. After updating the HPTE, we mark the
coresponding slot in the deposted PTE page valid.
Reviewed-by: David Gibson
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include
From: "Aneesh Kumar K.V"
We find all the overlapping vma and mark them such that we don't allocate
hugepage in that range. Also we split existing huge page so that the
normal page hash can be invalidated and new page faulted in with new
protection bits.
Signed-off-by: Aneesh Kumar K.V
---
arch
From: "Aneesh Kumar K.V"
GCC is very likely to read the pagetables just once and cache them in
the local stack or in a register, but it is can also decide to re-read
the pagetables. The problem is that the pagetable in those places can
change from under gcc.
With THP/hugetlbfs the pmd (and pgd f
From: "Aneesh Kumar K.V"
We need to have irqs disabled to handle all the possible parallel update for
linux page table without holding locks.
Events that we are intersted in while walking page tables are
1) Page fault
2) umap
3) THP split
4) THP collapse
A) local_irq_disabled:
-
From: "Aneesh Kumar K.V"
With THP we set pmd to none, before we do pte_clear. Hence we can't
walk page table to get the pte lock ptr and verify whether it is locked.
THP do take pte lock before calling pte_clear. So we don't change the locking
rules here. It is that we can't use page table walkin
From: "Aneesh Kumar K.V"
We enable only if the we support 16MB page size.
Reviewed-by: David Gibson
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/pgtable-ppc64.h | 3 +--
arch/powerpc/mm/pgtable_64.c | 29 +
2 files changed, 30 insertion
From: "Aneesh Kumar K.V"
Hugepage invalidate involves invalidating multiple hpte entries.
Optimize the operation using H_BULK_REMOVE on lpar platforms.
On native, reduce the number of tlb flush.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/machdep.h| 3 +
arch/powerpc/mm/
While we're restarting or powering off the system, we needn't
the OPAL notifier any more. So just to disable that.
Signed-off-by: Gavin Shan
---
arch/powerpc/platforms/powernv/setup.c |4
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/platforms/powernv/setup
This patch implements a notifier to receive a notification on OPAL
event mask changes. The notifier is only called as a result of an OPAL
interrupt, which will happen upon reception of FSP messages or PCI errors.
Any event mask change detected as a result of opal_poll_events() will not
result in a
The patch creates debugfs entries (powerpc/PCI/err_injct) for
injecting EEH errors for testing purpose.
Signed-off-by: Gavin Shan
---
arch/powerpc/platforms/powernv/eeh-ioda.c | 31 +
1 files changed, 31 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/p
It resends the last 5 patches ([27/31] - [31/31]) of the series to support EEH
for PowerNV platform.
v6 -> v7:
* Use atomic notifier to replace the original OPAL notifier according
to Ben's suggestion.
* Avoid registering duplicated notifiers for OPAL_EVENT_PCI_ERROR.
-
Ben,
As you mention just now, I resend this another pending patch sets v5 used
to support kgdb/gdb on book3e.
v5:
* rebase on merge branch.
Note the original patch, [ATCH 5/7] kgdb/kgdbts: support ppc64, is already
merged
by Jason.
v4:
* use DEFINE_PER_CPU to allocate kgdb's thread_info
* ad
We need to store thread info to these exception thread info like something
we already did for PPC32.
Signed-off-by: Tiejun Chen
---
arch/powerpc/kernel/exceptions-64e.S | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/powerpc/kernel/exceptions-64e.S
b/arch/powerpc/ker
We always alloc critical/machine/debug check exceptions. This is
different from the normal exception. So we should load these exception
stack properly like we did for booke.
Signed-off-by: Tiejun Chen
---
arch/powerpc/kernel/exceptions-64e.S | 49 +++---
1 file chan
Currently we need to skip this for supporting KGDB.
Signed-off-by: Tiejun Chen
---
arch/powerpc/kernel/exceptions-64e.S |4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/kernel/exceptions-64e.S
b/arch/powerpc/kernel/exceptions-64e.S
index 07cf657..a286b51 10
gdb always need to generate a single step properly to invoke
a kgdb state. But with lazy interrupt, book3e can't always
trigger a debug exception with a single step since the current
is blocked for handling those pending exception, then we miss
that expected dbcr configuration at last to generate a
Use DEFINE_PER_CPU to allocate thread_info statically instead of kmalloc().
This can avoid introducing more memory check codes.
Signed-off-by: Tiejun Chen
---
arch/powerpc/kernel/kgdb.c |5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/kernel/kgdb.c b/arch/
On Thu, Jun 20, 2013 at 06:13:21PM +0800, Gavin Shan wrote:
>
>It resends the last 5 patches ([27/31] - [31/31]) of the series to support EEH
>for PowerNV platform.
>
>v6 -> v7:
> * Use atomic notifier to replace the original OPAL notifier according
> to Ben's suggestion.
> * Av
When we're in kgdb_singlestep(), we have to work around to get
thread_info by copying from the kernel stack before calling
kgdb_handle_exception(), then copying it back afterwards.
But for PPC64, we have a lazy interrupt implementation. So after
copying thread info frome kernle stack, if we need t
The patch creates one debugfs directory ("powerpc/PCI") for
each PHB so that we can hook EEH error injection debugfs entry
there in proceeding patch.
Signed-off-by: Gavin Shan
---
arch/powerpc/platforms/powernv/pci-ioda.c | 23 +++
arch/powerpc/platforms/powernv/pci.h
The patch registers OPAL event notifier and process the PCI errors
from firmware. If we have pending PCI errors, special EEH event
(without binding PE) will be sent to EEH core for processing.
Signed-off-by: Gavin Shan
---
arch/powerpc/platforms/powernv/eeh-ioda.c | 41
Hi Scott,
Thanks for the reply, though a bit disheartening :-)
My understanding on e500 MMU is not clear. It'd be nice if I could find some
way (may be ad-hoc) to debug some use-after-free page corruptions. SLAB
debug tells me the page was modified by someone after it was freed but
DEBUG_PAGEALLOC
> I think we should be able to do something better using the C
> preprocessor, this is exactly the sort of thing it's good at.
>
> What I mean is something like we do with arch/powerpc/include/asm/systbl.h,
> where we define the list of syscalls once, and then include it in
> multiple places, usin
Varun,
On Wed, Apr 24, 2013 at 05:05:50PM +0530, Varun Sethi wrote:
> Added the following domain attributes for the FSL PAMU driver:
> 1. Added new iommu stash attribute, which allows setting of the
>LIODN specific stash id parameter through IOMMU API.
> 2. Added an attribute for enabling/disa
Hi Joerg,
My PAMU driver patches depend on this patch which was Ack by Kumar. Should I
resubmit this patch as well?
Regards
Varun
> -Original Message-
> From: Kumar Gala [mailto:ga...@kernel.crashing.org]
> Sent: Thursday, April 11, 2013 11:46 PM
> To: Sethi Varun-B16395
> Cc: j...@8byte
On Thu, Jun 20, 2013 at 02:29:30PM +, Sethi Varun-B16395 wrote:
> Hi Joerg,
> My PAMU driver patches depend on this patch which was Ack by Kumar. Should I
> resubmit this patch as well?
Yes, please. Add the collected Acked-bys and submit everything that is
missing in v3.10-rc6.
Joer
On Thu, 2013-06-20 at 18:48 +1000, Alexey Kardashevskiy wrote:
> On 06/20/2013 05:47 PM, Benjamin Herrenschmidt wrote:
> > On Thu, 2013-06-20 at 15:28 +1000, David Gibson wrote:
> >>> Just out of curiosity - would not get_file() and fput_atomic() on a
> >> group's
> >>> file* do the right job inste
Added the following domain attributes for the FSL PAMU driver:
1. Added new iommu stash attribute, which allows setting of the
LIODN specific stash id parameter through IOMMU API.
2. Added an attribute for enabling/disabling DMA to a particular
memory window.
3. Added domain attribute to chec
Add an iommu domain pointer to device (powerpc) archdata. Devices
are attached to iommu domains and this pointer provides a mechanism
to correlate between a device and the associated iommu domain. This
field is set when a device is attached to a domain.
Signed-off-by: Varun Sethi
Acked-by: Kuma
On 06/20/2013 05:42:40 AM, perth1415 wrote:
Hi Scott,
Thanks for the reply, though a bit disheartening :-)
My understanding on e500 MMU is not clear. It'd be nice if I could
find some
way (may be ad-hoc) to debug some use-after-free page corruptions.
SLAB
debug tells me the page was modifie
On some PAE architectures, the entire range of physical memory could reside
outside the 32-bit limit. These systems need the ability to specify the
initrd location using 64-bit numbers.
This patch globally modifies the early_init_dt_setup_initrd_arch() function to
use 64-bit numbers instead of th
Hi Santosh,
On 06/21/2013 06:22 AM, Santosh Shilimkar wrote:
> Cc: Vineet Gupta
> Cc: Russell King
> Cc: Catalin Marinas
> Cc: Will Deacon
> Cc: Mark Salter
> Cc: Aurelien Jacquiot
> Cc: James Hogan
> Cc: Michal Simek
> Cc: Ralf Baechle
> Cc: Jonas Bonn
> Cc: Benjamin Herrenschmidt
> Cc
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