Hi Ian,
On 04/24/2013 12:48 PM, Ian Campbell wrote:
> Hi,
>
> First off apologies for the large CC list -- I think this catches the
> arch list for all the arches with device tree source in the tree.
>
> Various folks have expressed an interest in eventually splitting the
> device tree bindings
David Woodhouse wrote:
> From: David Woodhouse
>
> Some versions of GCC apparently expect this to be provided by libgcc.
>
> Signed-off-by: David Woodhouse
> ---
> Untested.
>
> diff --git a/arch/powerpc/kernel/misc_32.S b/arch/powerpc/kernel/misc_32.S
> index 19e096b..f077dc2 100644
> --- a
From: David Woodhouse
Some versions of GCC apparently expect this to be provided by libgcc.
Updates from Mikey to fix 32 bit version and adding "r" to registers.
Signed-off-by: David Woodhouse
Signed-off-by: Michael Neuling
diff --git a/arch/powerpc/kernel/misc_32.S b/arch/powerpc/kernel/mis
On Mon, May 13, 2013 at 04:48:19PM +1000, Anton Blanchard wrote:
> On Fri, 10 May 2013 22:18:27 +0100
> David Woodhouse wrote:
>
> > From: David Woodhouse
> >
> > Some versions of GCC apparently expect this to be provided by libgcc.
>
> Thanks Dave. We were discussing this with Alan Modra and
On Mon, 2013-05-13 at 15:51 +1000, Benjamin Herrenschmidt wrote:
> On Mon, 2013-05-13 at 13:21 +0800, Li Zhong wrote:
> > These patches try to support context tracking for Power arch, beginning with
> > 64-bit pSeries. The codes are ported from that of the x86_64, and in each
> > patch, I listed th
On Mon, May 13, 2013 at 05:09:59PM +1000, Michael Neuling wrote:
> David Woodhouse wrote:
>
> > From: David Woodhouse
> >
> > Some versions of GCC apparently expect this to be provided by libgcc.
> >
> > Signed-off-by: David Woodhouse
> > ---
> > Untested.
> >
> > diff --git a/arch/powerpc/k
On Mon, 2013-05-13 at 15:57 +1000, Benjamin Herrenschmidt wrote:
> On Mon, 2013-05-13 at 13:21 +0800, Li Zhong wrote:
> > int recover = 0;
> > + enum ctx_state prev_state;
> > +
> > + prev_state = exception_enter();
>
> Please make it nicer:
>
> enum ctx_state prev_state = exception
On Mon, 2013-05-13 at 16:03 +0800, Li Zhong wrote:
>
> To my understanding, it is used to enable RCU user extended quiescent
> state, so RCU on that cpu doesn't need scheduler ticks. And together
> with some other code(already in 3.10), we are able to remove the ticks
> in some cases (e.g. only 1
On Mon, 2013-05-13 at 16:44 +0800, Li Zhong wrote:
> Yes, the above and hash_page() are two C functions for a same exception.
> And the exception hooks enable RCU usage in those C codes. But for asm
> codes, I think we could assume that there would be no RCU usage there,
> so we don't need wrap the
On Mon, 2013-05-13 at 18:59 +1000, Benjamin Herrenschmidt wrote:
> On Mon, 2013-05-13 at 16:03 +0800, Li Zhong wrote:
> >
> > To my understanding, it is used to enable RCU user extended quiescent
> > state, so RCU on that cpu doesn't need scheduler ticks. And together
> > with some other code(alre
On Mon, 2013-05-13 at 19:06 +1000, Benjamin Herrenschmidt wrote:
> On Mon, 2013-05-13 at 16:44 +0800, Li Zhong wrote:
> > Yes, the above and hash_page() are two C functions for a same exception.
> > And the exception hooks enable RCU usage in those C codes. But for asm
> > codes, I think we could a
On Mon, 2013-05-13 at 17:46 +0800, Li Zhong wrote:
> > hash_page() won't start a new RCU, at least not in its current incarnation,
> > the only thing I can see it ever doing would be to take some RCU read locks
> > one
> > day (it doesn't today).
>
> Seems I added the hooks because of the trace p
From: David Woodhouse
Some versions of GCC apparently expect this to be provided by libgcc.
Updates from Mikey to fix 32 bit version and adding "r" to registers.
Signed-off-by: David Woodhouse
Signed-off-by: Michael Neuling
---
Fixes from Gabriel.
arch/powerpc/kernel/misc_32.S | 11
On Mon, 2013-05-13 at 16:50 +0930, Alan Modra wrote:
> I did a little digging, and it looks like gcc-4.4 will emit __bswapdi2
> calls. Support in rs6000.md appeared 2009-06-25.
That's where it was seen. I don't have anything that ancient any more so
it didn't show up in my testing, but Al saw it
On Mon, 2013-05-13 at 17:09 +1000, Michael Neuling wrote:
>
> This doesn't work for me but the below does:
...
>
> stolen from GCC -02 output of:
> unsigned long long __bswapdi2(unsigned long long x)
Hm, so was mine:
[dwmw2@i7 ~]$ powerpc64-linux-gnu-gcc -O2 -S -o- bswapdi2.c -m32
.f
On Mon, 2013-05-13 at 11:33 +0100, David Woodhouse wrote:
>
> On Mon, 2013-05-13 at 09:33 +0200, Gabriel Paubert wrote:
> > Actually, I'd swap the two mr instructions to never
> > have an instruction that uses the result from the
> > previous one.
>
> Bad GCC. No biscuit.
>
> Should we file a P
"Linuxppc-dev"
wrote 2013/05/13 12:38:13:
>
> On Mon, 2013-05-13 at 11:33 +0100, David Woodhouse wrote:
> >
> > On Mon, 2013-05-13 at 09:33 +0200, Gabriel Paubert wrote:
> > > Actually, I'd swap the two mr instructions to never
> > > have an instruction that uses the result from the
> > > prev
"Linuxppc-dev"
wrote on 2013/05/13 12:51:59:
>
> "Linuxppc-dev"
>
> wrote 2013/05/13 12:38:13:
> >
> > On Mon, 2013-05-13 at 11:33 +0100, David Woodhouse wrote:
> > >
> > > On Mon, 2013-05-13 at 09:33 +0200, Gabriel Paubert wrote:
> > > > Actually, I'd swap the two mr instructions to never
On Mon, 2013-05-13 at 08:02 +0100, Michal Simek wrote:
> Just small overview it is a Xilinx soft core cpu where you can even setup
> some parameters for core itself - multiplier, divider, BS, fpu, cache sizes,
> etc.
> You have to also compose the whole system and every platform/configuration is
Hi Ben,
This fix is trivial. Just compile-tested it.
Alexander Gordeev (1):
powerpc: Fix irq_set_affinity() return values
arch/powerpc/platforms/wsp/ics.c|2 +-
arch/powerpc/sysdev/ehv_pic.c |2 +-
arch/powerpc/sysdev/mpic.c |2 +-
arch/powerpc/sysdev/xics/ics-o
Signed-off-by: Alexander Gordeev
---
arch/powerpc/platforms/wsp/ics.c|2 +-
arch/powerpc/sysdev/ehv_pic.c |2 +-
arch/powerpc/sysdev/mpic.c |2 +-
arch/powerpc/sysdev/xics/ics-opal.c |2 +-
4 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/powe
On Mon, May 13, 2013 at 11:38:13AM +0100, David Woodhouse wrote:
> On Mon, 2013-05-13 at 11:33 +0100, David Woodhouse wrote:
> >
> > On Mon, 2013-05-13 at 09:33 +0200, Gabriel Paubert wrote:
> > > Actually, I'd swap the two mr instructions to never
> > > have an instruction that uses the result fr
On 05/11/2013 06:26:21 PM, Kevin Hao wrote:
In the external proxy facility mode, the interrupt is automatically
acknowledged with the same effect as reading the IACK register. So
this makes external input interrupt more like edge sensitive. That
means we can leave the irq hard enabled when it occ
On 05/13/2013 01:59 PM, Ian Campbell wrote:
> On Mon, 2013-05-13 at 08:02 +0100, Michal Simek wrote:
>> Just small overview it is a Xilinx soft core cpu where you can even setup
>> some parameters for core itself - multiplier, divider, BS, fpu, cache sizes,
>> etc.
>> You have to also compose the
From: Gu Zheng
From: Gu Zheng
Use the new pci_alloc_dev(bus) to replace the existing using of
alloc_pci_dev(void).
v2:
Follow Bjorn's correction to move pci_bus_put() to
pci_release_dev() instead.
Signed-off-by: Gu Zheng
Cc: Benjamin Herrenschmidt
Cc: Paul Mackerras
Cc: "David S. Mill
I did a little digging, and it looks like gcc-4.4 will emit
__bswapdi2
calls. Support in rs6000.md appeared 2009-06-25.
That's where it was seen. I don't have anything that ancient any
more so
it didn't show up in my testing, but Al saw it on a Debian system.
It should never happen on 32
rlwinm 10,4,8,0x
rlwinm 11,3,8,0x
rlwimi 10,4,24,0,7
rlwimi 11,3,24,0,7
rlwimi 10,4,24,16,23
rlwimi 11,3,24,16,23
mr 4,11
mr 3,10
Actually, I'd swap the two mr instructions to never
have an instruction that uses the
On Mon, May 13, 2013 at 9:08 AM, Jiang Liu wrote:
> From: Gu Zheng
> diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
> index 4f0bc0a..bc075a3 100644
> --- a/drivers/pci/probe.c
> +++ b/drivers/pci/probe.c
> @@ -1131,6 +1131,7 @@ static void pci_release_dev(struct device *dev)
> str
Quoting yuantian.t...@freescale.com (2013-04-09 01:46:26)
> From: Tang Yuantian
>
> This adds the clock driver for Freescale PowerPC corenet
> series SoCs using common clock infrastructure.
>
> Signed-off-by: Tang Yuantian
> Signed-off-by: Li Yang
Patch #1 looks good to me. I've taken it int
Erratum A-006037 indicates I2C controller executes the write to I2CCR only
after it sees SCL idle for 64K cycle of internal I2C controller clocks. If
during this waiting period, I2C controller is disabled (I2CCR[MEN] set to
0), then the controller could end in bad state, and hang the future access
MSR_DE is not cleared on entry to the kernel, and we don't clear it
explicitly outside of debug code. If we have MSR_DE set in
prime_debug_regs(), and the new thread has events enabled in DBCR0
(e.g. ICMP is set in thread->dbsr0, even though it was cleared in the
real DBCR0 when the thread got sc
Hi Mikey,
On Mon, 13 May 2013 17:09:59 +1000 Michael Neuling wrote:
>
> This doesn't work for me but the below does:
>
> _GLOBAL(__bswapdi2)
> rotlwi r9,r4,8
> rotlwi r10,r3,8
> rlwimi r9,r4,24,0,7
> rlwimi r10,r3,24,0,7
> rlwimi r9,r4,24,16,23
> rlwimi
On 14 May 2013 11:09, "Stephen Rothwell" wrote:
>
> Hi Mikey,
>
> On Mon, 13 May 2013 17:09:59 +1000 Michael Neuling
wrote:
> >
> > This doesn't work for me but the below does:
> >
> > _GLOBAL(__bswapdi2)
> > rotlwi r9,r4,8
> > rotlwi r10,r3,8
> > rlwimi r9,r4,24,0,7
> >
On Mon, May 13, 2013 at 10:47:17AM -0500, Scott Wood wrote:
> On 05/11/2013 06:26:21 PM, Kevin Hao wrote:
> >In the external proxy facility mode, the interrupt is automatically
> >acknowledged with the same effect as reading the IACK register. So
> >this makes external input interrupt more like edg
These patches try to support context tracking for Power arch, beginning with
64-bit pSeries. The codes are ported from that of the x86_64, and in each
patch, I listed the corresponding patch for x86.
v4:
fixed some cosmetic issues suggested by Ben.
Li Zhong (5):
powerpc: Syscall hooks for conte
This is the syscall slow path hooks for context tracking subsystem,
corresponding to
[PATCH] x86: Syscall hooks for userspace RCU extended QS
commit bf5a3c13b939813d28ce26c01425054c740d6731
TIF_MEMDIE is moved to the second 16-bits (with value 17), as it seems there
is no asm code using it. TIF_
This is the exception hooks for context tracking subsystem, including
data access, program check, single step, instruction breakpoint, machine check,
alignment, fp unavailable, altivec assist, unknown exception, whose handlers
might use RCU.
This patch corresponds to
[PATCH] x86: Exception hooks f
This patch allows RCU usage in do_notify_resume, e.g. signal handling.
It corresponds to
[PATCH] x86: Exit RCU extended QS on notify resume
commit edf55fda35c7dc7f2d9241c3abaddaf759b457c6
Signed-off-by: Li Zhong
---
arch/powerpc/kernel/signal.c |5 +
1 file changed, 5 insertions(+)
di
This patch corresponds to
[PATCH] x86: Use the new schedule_user API on userspace preemption
commit 0430499ce9d78691f3985962021b16bf8f8a8048
Signed-off-by: Li Zhong
---
arch/powerpc/include/asm/context_tracking.h | 10 ++
arch/powerpc/kernel/entry_64.S |3 ++-
2 file
Start context tracking support from pSeries.
Signed-off-by: Li Zhong
---
arch/powerpc/platforms/pseries/Kconfig |1 +
1 file changed, 1 insertion(+)
diff --git a/arch/powerpc/platforms/pseries/Kconfig
b/arch/powerpc/platforms/pseries/Kconfig
index 9a0941b..023b288 100644
--- a/arch/powerpc
v3 changes:
Don't break 32 bit
v2 changes:
add __user to ptr to __get_user_inatomic()
Michael Neuling (3):
powerpc/perf: Move BHRB code into CONFIG_PPC64 region
powerpc/pmu: Fix order of interpreting BHRB target entries
powerpc/perf: Fix setting of "to" addresses for BHRB
arch/powerp
The new Branch History Rolling buffer (BHRB) code is only useful on 64bit
processors, so move it into the #ifdef CONFIG_PPC64 region.
This avoids code bloat on 32bit systems.
Signed-off-by: Michael Neuling
---
arch/powerpc/perf/core-book3s.c | 248 ---
1 fil
The current Branch History Rolling Buffer (BHRB) code misinterprets the order
of entries in the hardware buffer. It assumes that a branch target address
will be read _after_ its corresponding branch. In reality the branch target
comes before (lower mfbhrb entry) it's corresponding branch.
This i
Currently we only set the "to" address in the branch stack when the CPU
explicitly gives us a value. Unfortunately it only does this for XL form
branches (eg blr, bctr, bctar) and not I and B form branches (eg b, bc).
Fortunately if we read the instruction from memory we can extract the offset of
Future firmwares will support that new version. We need that
to properly fix CPU starting under OPAL with kexec.
Signed-off-by: Benjamin Herrenschmidt
---
arch/powerpc/include/asm/firmware.h|4 +++-
arch/powerpc/include/asm/opal.h|3 ++-
arch/powerpc/platforms/powernv/opal.c
The current code fails to handle kexec on OPALv2. This fixes it
and adds code to improve the situation on OPALv3 where we can
query the CPU status from the firmware and decide what to do
based on that.
Signed-off-by: Benjamin Herrenschmidt
---
arch/powerpc/platforms/powernv/smp.c | 62
On Tue, 2013-05-14 at 11:25 +1000, Michael Neuling wrote:
>
> > So, if we are just stealing the output of gcc, why not just use the C
> > version (at least for 32 bit)?
>
> Woodhouse: can we just do this?
Sure, if you don't mind GCC optimising the contents of your C function
by turning it into a
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