> -Original Message-
> From: Joerg Roedel [mailto:j...@8bytes.org]
> Sent: Tuesday, April 02, 2013 9:48 PM
> To: Sethi Varun-B16395
> Cc: Yoder Stuart-B08248; Wood Scott-B07421; iommu@lists.linux-
> foundation.org; linuxppc-dev@lists.ozlabs.org; linux-
> ker...@vger.kernel.org; ga...@kern
Hi Kumar,
what about this patch? Any reasons not to apply?
Rojhalat
On Monday 18 March 2013 10:22:40 Rojhalat Ibrahim wrote:
> On Thursday 14 March 2013 15:35:40 Kumar Gala wrote:
> > On Mar 14, 2013, at 4:43 AM, Rojhalat Ibrahim wrote:
> > > On Wednesday 13 March 2013 14:07:16 Kumar Gala wr
On Wed, Apr 03, 2013 at 05:21:16AM +, Sethi Varun-B16395 wrote:
> > I would prefer these PAMU specific enum and struct to be in a pamu-
> > specific iommu-header.
> >
>
> [Sethi Varun-B16395] But, these would be used by the IOMMU API users
> (e.g. VFIO), they shouldn't depend on PAMU specific
On 31 March 2013 09:33, Viresh Kumar wrote:
> On 25 March 2013 22:24, Viresh Kumar wrote:
>> This patch moves cpufreq driver of powerpc platform to drivers/cpufreq.
>>
>> Cc: Benjamin Herrenschmidt
>> Cc: Paul Mackerras
>> Cc: Olof Johansson
>> Cc: linuxppc-dev@lists.ozlabs.org
>> Signed-off-b
On Wed, 2013-04-03 at 15:00 +0530, Viresh Kumar wrote:
> On 31 March 2013 09:33, Viresh Kumar wrote:
> > On 25 March 2013 22:24, Viresh Kumar wrote:
> >> This patch moves cpufreq driver of powerpc platform to drivers/cpufreq.
> >>
> >> Cc: Benjamin Herrenschmidt
> >> Cc: Paul Mackerras
> >> Cc:
On 3 April 2013 16:00, Benjamin Herrenschmidt wrote:
> I'm on vacation until end of April. No objection to the patch but
> somebody needs to test it.
Any input on whom i can ask for that?
___
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Linuxppc-dev@lists.ozlabs.org
https
From: Chen-Hui Zhao
The bootloader have done time base sync for all cores, so skip
the synchronization process at boot time of kernel.
Signed-off-by: Zhao Chenhui
Signed-off-by: Li Yang
Signed-off-by: Andy Fleming
---
arch/powerpc/platforms/85xx/smp.c |8
1 files changed, 8 inse
From: Chen-Hui Zhao
mpic_reset_core() need a logical cpu number instead of physical.
Signed-off-by: Zhao Chenhui
Signed-off-by: Li Yang
---
arch/powerpc/platforms/85xx/smp.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/platforms/85xx/smp.c
b/arch/pow
These cache operations support Freescale SoCs based on BOOK3E.
Move L1 cache operations to fsl_booke_cache.S in order to maintain
easily. And, add cache operations for backside L2 cache and platform cache.
The backside L2 cache appears on e500mc and e5500 core. The platform cache
supported by this
Some Freescale SoCs like MPC8536 and P1022 has the deep sleep mode
in addtion to the sleep mode.
In sleep PM mode, the clocks of e500 core and unused IP blocks is
turned off. IP blocks which are allowed to wake up the processor
are still running.
While in deep sleep PM mode, additionally, the pow
From: chenhui zhao
Add APIs for setting wakeup source and lossless Ethernet in low power modes.
These APIs can be used by wake-on-packet feature.
Signed-off-by: Dave Liu
Signed-off-by: Li Yang
Signed-off-by: Jin Qing
Signed-off-by: Zhao Chenhui
---
arch/powerpc/sysdev/fsl_pmc.c | 71 +
The Power Management device tree stub indicated that the platform
supports Power Management feature.
Signed-off-by: Zhao Chenhui
---
arch/powerpc/boot/dts/fsl/mpc8536si-post.dtsi | 14 ++-
arch/powerpc/boot/dts/fsl/mpc8544si-post.dtsi |2 +
arch/powerpc/boot/dts/fsl/mpc8548si-post.dtsi
From: Li Yang
Signed-off-by: Li Yang
Signed-off-by: Zhao Chenhui
---
.../devicetree/bindings/powerpc/fsl/pmc.txt| 59 +++
1 files changed, 34 insertions(+), 25 deletions(-)
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/pmc.txt
b/Documentation/devicetree
From: chenhui zhao
Some MPC85xx SoCs like MPC8536 and P1022 have a JOG feature, which provides
a dynamic mechanism to lower or raise the CPU core clock at runtime.
This patch adds the support to change CPU frequency using the standard
cpufreq interface. The ratio CORE to CCB can be 1:1(except MP
From: Chen-Hui Zhao
In the case of SMP, during the time base sync period, all time bases of
online cores must stop, then start simultaneously.
There is a RCPM (Run Control/Power Management) module in CoreNet based SoCs.
Define a struct ccsr_rcpm to describe the register map.
This patch supports
From: Chen-Hui Zhao
Add support to disable and re-enable individual cores at runtime.
This supports e500mc/e5500 core based SoCs.
To prevent the register access race, only read/write RCPM registers
in platform_cpu_die() on the boot cpu instead of accessing by individual
cpus. Platform implementa
The SoCs which have a RCPM (Run Control/Power Management) module
support power management feature. This patch implements sleep feature.
In sleep mode, the clocks of cores and unused IP blocks will be
turned off. The IP blocks which are allowed to wake up the system
are still running.
Signed-off-b
From: Chen-Hui Zhao
* The paca[cpu].cpu_start is used as a signal to indicate if the cpu
should start. So it should be cleard in .cpu_die().
* The limit memory routine only needs to be ran once at boot time
by the boot cpu. Prevent other cpus running it again.
* Rearrange the code segment in
From: Chen-Hui Zhao
Add struct ccsr_rcpm_v2 to descibe the v2 RCPM register map on some SoCs,
such as T4240, etc.
Signed-off-by: Zhao Chenhui
Signed-off-by: Li Yang
Signed-off-by: Andy Fleming
---
arch/powerpc/include/asm/fsl_guts.h | 66 +++
1 files changed
From: Chen-Hui Zhao
The L1 Data Cache of e6500 contains no modified data, no flush
is required.
Signed-off-by: Zhao Chenhui
Signed-off-by: Li Yang
Signed-off-by: Andy Fleming
---
arch/powerpc/kernel/fsl_booke_cache.S | 11 ++-
1 files changed, 10 insertions(+), 1 deletions(-)
diff
From: Chen-Hui Zhao
For e6500, two threads in one core share one time base. Just need
to do time base sync on first thread of one core, and skip it on
the other thread.
Signed-off-by: Zhao Chenhui
Signed-off-by: Li Yang
Signed-off-by: Andy Fleming
---
arch/powerpc/platforms/85xx/smp.c | 52
From: Chen-Hui Zhao
* Only if two threads of one core are offline, the core can
enter PH20 state.
* Clear PH20 bits before core reset, or core will not restart.
* Introduced a variable l2cache_type in the struce cpu_spec to
indentify the type of L2 cache.
Signed-off-by: Zhao Chenhui
Signed-
From: Chen-Hui Zhao
RCPM unit controls the power managment of T4/B4 chips. Software can
access RCPM registers to put specific thread/core in PH10/PH15/PH20/PH30
state or put the device in LPM10/LPM20/LPM40 mode.
The RCPM unit supports several wake up sources through internal timers
and internal
On Apr 3, 2013, at 8:09 AM, Zhao Chenhui wrote:
> From: Chen-Hui Zhao
>
> The bootloader have done time base sync for all cores, so skip
> the synchronization process at boot time of kernel.
>
> Signed-off-by: Zhao Chenhui
> Signed-off-by: Li Yang
> Signed-off-by: Andy Fleming
> ---
> arch/
Hi All,
The kernel exception handling code for 32 bit (transfer_to_handler in
entry_32.S) clear DBSR and load DBCR0 with 0 (global_dbcr0 variable, which is
zero) if user space used debug (DBCR0.IDM set).
But I do not same (clearing DBCR0 and DBSR) in 64bit exception handler. Is this
an issue o
> -Original Message-
> From: Sethi Varun-B16395
> Sent: Wednesday, April 03, 2013 12:12 AM
> To: Wood Scott-B07421; Timur Tabi
> Cc: Joerg Roedel; lkml; Kumar Gala; Yoder Stuart-B08248;
> io...@lists.linux-foundation.org; Benjamin
> Herrenschmidt; linuxppc-dev@lists.ozlabs.org
> Subject:
On Apr 3, 2013, at 10:24 AM, Bhushan Bharat-R65777 wrote:
> Hi All,
>
> The kernel exception handling code for 32 bit (transfer_to_handler in
> entry_32.S) clear DBSR and load DBCR0 with 0 (global_dbcr0 variable, which is
> zero) if user space used debug (DBCR0.IDM set).
>
> But I do not same
On 04/02/2013 09:03:17 PM, Jia Hongtao wrote:
MPIC version is useful information for both mpic_alloc() and
mpic_init().
The patch provide an API to get MPIC version for reusing the code.
Also, some other IP block may need MPIC version for their own use.
The API for external use is also provided
On 04/03/2013 01:42:14 AM, Leekha Shaveta-B20052 wrote:
-Original Message-
From: Wood Scott-B07421
Sent: Wednesday, April 03, 2013 12:49 AM
To: Leekha Shaveta-B20052
Cc: linuxppc-dev@lists.ozlabs.org; Zhao Chenhui-B35336; Lian
Minghuan-B31939; Leekha Shaveta-B20052; Garg Vakul-B16394;
On Apr 2, 2013, at 2:16 AM, Shaveta Leekha wrote:
> B4860 and B4420 are similar that share some commonalities
>
> * common features have been added in b4si-pre.dtsi and b4si-post.dtsi
> * differences are added in respective silicon files of B4860 and B4420
What are the differences between B4860
On Apr 2, 2013, at 2:16 AM, Shaveta Leekha wrote:
> - Add support for B4 board in board file b4_qds.c,
> It is common for B4860, B4420 and B4220QDS as they share same QDS board
> - Add B4QDS support in Kconfig and Makefile
>
> B4860QDS is a high-performance computing evaluation, development and
On Mar 18, 2013, at 6:19 PM, Ben Collins wrote:
> Somehow the driver snuck in with these still in it.
>
> Signed-off-by: Ben Collins
> ---
> arch/powerpc/platforms/85xx/sgy_cts1000.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
applied to next
- k
On Apr 3, 2013, at 8:09 AM, Zhao Chenhui wrote:
> From: Chen-Hui Zhao
>
> mpic_reset_core() need a logical cpu number instead of physical.
>
> Signed-off-by: Zhao Chenhui
> Signed-off-by: Li Yang
> ---
> arch/powerpc/platforms/85xx/smp.c |2 +-
> 1 files changed, 1 insertions(+), 1 deleti
On Apr 2, 2013, at 8:33 AM, Sebastian Andrzej Siewior wrote:
> lockdep thinks that it might deadlock because it grabs a lock of the
> same class while calling the generic_irq_handler(). This annotation will
> inform lockdep that it will not.
>
> Signed-off-by: Sebastian Andrzej Siewior
> ---
>
On Apr 2, 2013, at 2:14 AM, wrote:
> From: Shaveta Leekha
>
> Signed-off-by: Vakul Garg
> Signed-off-by: Shaveta Leekha
> ---
> arch/powerpc/boot/dts/fsl/qoriq-sec5.3-0.dtsi | 118 +
> 1 files changed, 118 insertions(+), 0 deletions(-)
> create mode 100644 arch/power
> -Original Message-
> From: Kumar Gala [mailto:ga...@kernel.crashing.org]
> Sent: Wednesday, April 03, 2013 9:41 PM
> To: Bhushan Bharat-R65777
> Cc: linuxppc-dev@lists.ozlabs.org; Benjamin Herrenschmidt; Alexander Graf;
> Wood
> Scott-B07421
> Subject: Re: Clearing DBSR and DBCR0 in ho
On Tue, 2013-04-02 at 18:18 +0200, Joerg Roedel wrote:
> Cc'ing Alex Williamson
>
> Alex, can you please review the iommu-group part of this patch?
Sure, it looks pretty reasonable. AIUI, all PCI devices are below some
kind of host bridge that is either new and supports partitioning or old
and d
On Mar 29, 2013, at 8:06 AM, Roy Zang wrote:
> The size might be 64 bit, so use ilog2() instead of __ilog2() or
> __ilog2_u64().
>
> ilog2() can select 32bit or 64bit funciton automatically.
>
> Signed-off-by: Roy Zang
> ---
> arch/powerpc/sysdev/fsl_pci.c | 10 +-
> 1 file changed, 5
On 04/03/2013 12:36:41 AM, Wang Dongsheng-B40534 wrote:
> -Original Message-
> From: Wood Scott-B07421
> Sent: Wednesday, April 03, 2013 8:35 AM
> To: Wang Dongsheng-B40534
> Cc: Wood Scott-B07421; Johannes Berg; linuxppc-dev@lists.ozlabs.org
> Subject: Re: [PATCH] powerpc: add Book E s
On 04/03/2013 05:07:30 PM, Scott Wood wrote:
On 04/03/2013 04:58:56 PM, Alexander Graf wrote:
Am 03.04.2013 um 23:38 schrieb Scott Wood :
> On 04/03/2013 11:19:42 AM, Alexander Graf wrote:
>> On 03.04.2013, at 03:57, Scott Wood wrote:
>> > +switch (attr->group) {
>> > +case KVM_DEV_MP
On 03/04/2013 02:20 AM, Qiang Liu wrote:
Support config RX WATER MARK via sysfs when running at run-time;
A wrokaround for fix the exception happened to some WD HDD, found on
WD3000HLFS-01G6U1, WD3000HLFS-01G6U0, some SSD disks. The read performance
is also regression (about 30%) when use default
No other reason. Just avoid doing it again at boot time in kernel.
-Chenhui
From: Kumar Gala [ga...@kernel.crashing.org]
Sent: Wednesday, April 03, 2013 23:10
To: Zhao Chenhui-B35336
Cc: linuxppc-dev@lists.ozlabs.org
Subject: Re: [PATCH 02/17] powerpc/85x
On Mon, Mar 25, 2013 at 01:52:32PM -0500, Nathan Fontenot wrote:
> From: Jesse Larrew
>
> A PRRN event is signaled via the RTAS event-scan mechanism, which
> returns a Hot Plug Event message "fixed part" indicating "Platform
> Resource Reassignment". In response to the Hot Plug Event message,
> w
On Mon, Mar 25, 2013 at 01:54:54PM -0500, Nathan Fontenot wrote:
> The firmware_has_feature() function makes it easy to check for supported
> features of the hypervisor. This patch extends the capability of the
> firmware_has_feature() function to include checking for specified bits
> in vector 5 o
On Mon, Mar 25, 2013 at 01:51:38PM -0500, Nathan Fontenot wrote:
> From: Jesse Larrew
>
> Newer firmware on Power systems can transparently reassign platform resources
> (CPU and Memory) in use. For instance, if a processor or memory unit is
> predicted to fail, the platform may transparently mov
On Mon, Mar 25, 2013 at 01:56:05PM -0500, Nathan Fontenot wrote:
> Update the numa code to use the updated firmware_has_feature() when checking
> for type 1 affinity.
>
> Signed-off-by: Nathan Fontenot
Acked-by: Paul Mackerras
___
Linuxppc-dev mailing
On Mon, Mar 25, 2013 at 01:57:08PM -0500, Nathan Fontenot wrote:
> From: Jesse Larrew
>
> Platform events such as partition migration or the new PRRN firmware
> feature can cause the NUMA characteristics of a CPU to change, and these
> changes will be reflected in the device tree nodes for the af
On Mon, Mar 25, 2013 at 01:58:04PM -0500, Nathan Fontenot wrote:
> From: Jesse Larrew
>
> The new PRRN firmware feature allows CPU and memory resources to be
> transparently reassigned across NUMA boundaries. When this happens, the
> kernel must update the node maps to reflect the new affinity
>
From: "Aneesh Kumar K.V"
PAPR defines these errors as negative values. So print them accordingly
for easy debugging.
Acked-by: Paul Mackerras
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/platforms/pseries/lpar.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/p
From: "Aneesh Kumar K.V"
This patch moves the common code to 32/64 bit headers and also duplicate
4K_PAGES and 64K_PAGES section. We will later change the 64 bit 64K_PAGES
version to support smaller PTE fragments. The patch doesn't introduce
any functional changes.
Acked-by: Paul Mackerras
Sign
From: "Aneesh Kumar K.V"
We were not saving DAR and DSISR on MCE. Save then and also print the values
along with exception details in xmon.
Acked-by: Paul Mackerras
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/kernel/exceptions-64s.S |9 +
arch/powerpc/xmon/xmon.c
Hi,
This patchset adds transparent hugepage support for PPC64.
TODO:
* hash preload support in update_mmu_cache_pmd (we don't do that for hugetlb)
Some numbers:
The latency measurements code from Anton found at
http://ozlabs.org/~anton/junkcode/latency2001.c
THP disabled 64K page size
---
From: "Aneesh Kumar K.V"
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/mmu-hash64.h |3 ++-
arch/powerpc/mm/hash_utils_64.c | 12 +++-
arch/powerpc/mm/hugetlbpage-hash64.c |2 +-
3 files changed, 10 insertions(+), 7 deletions(-)
diff --git a/arch/powerpc
From: "Aneesh Kumar K.V"
This make one PMD cover 16MB range. That helps in easier implementation of THP
on power. THP core code make use of one pmd entry to track the hugepage and
the range mapped by a single pmd entry should be equal to the hugepage size
supported by the hardware.
Acked-by: Pau
From: "Aneesh Kumar K.V"
USE PTRS_PER_PTE to indicate the size of pte page. To support THP,
later patches will be changing PTRS_PER_PTE value.
Acked-by: Paul Mackerras
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/pgtable.h |6 ++
arch/powerpc/mm/hash_low_64.S |
From: "Aneesh Kumar K.V"
In all these cases we are doing something similar to
HPTE_V_COMPARE(hpte_v, want_v) which ignores the HPTE_V_LARGE bit
With MPSS support we would need actual page size to set HPTE_V_LARGE
bit and that won't be available in most of these cases. Since we are ignoring
HPTE
From: "Aneesh Kumar K.V"
This gives hint about different base and actual page size combination
supported by the platform.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/mm/hash_utils_64.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/mm/hash_ut
From: "Aneesh Kumar K.V"
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/kvm/book3s_hv.c | 14 --
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c
index 48f6d99..f472414 100644
--- a/arch/powerpc/kvm/book3s
From: "Aneesh Kumar K.V"
This make sure we handle multiple page size segment correctly.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/mm/hash_native_64.c | 30 --
1 file changed, 28 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/mm/hash_native_64.c b/
From: "Aneesh Kumar K.V"
We look at both the segment base page size and actual page size and store
the pte-lp-encodings in an array per base page size.
We also update all relevant functions to take actual page size argument
so that we can use the correct PTE LP encoding in HPTE. This should also
From: "Aneesh Kumar K.V"
As per ISA doc, we encode base and actual page size in the LP bits of
PTE. The number of bit used to encode the page sizes depend on actual
page size. ISA doc lists this as
PTE LP actual page size
rrrz >=8KB
rrzz >=16KB
rzzz >=32K
From: "Aneesh Kumar K.V"
On archs like powerpc that support different hugepage sizes, HPAGE_SHIFT
and other derived values like HPAGE_PMD_ORDER are not constants. So move
that to hugepage_init
Cc: Andrea Arcangeli
Signed-off-by: Aneesh Kumar K.V
---
include/linux/huge_mm.h |3 ---
mm/huge
From: "Aneesh Kumar K.V"
This will be later used by powerpc THP support. In powerpc we want to use
pgtable for storing the hash index values. So instead of adding them to
mm_context list, we would like to store them in the second half of pmd
Cc: Andrea Arcangeli
Signed-off-by: Aneesh Kumar K.V
From: "Aneesh Kumar K.V"
For architectures like ppc64 we look at deposited pgtable when
calling pmdp_get_and_clear. So do the pgtable_trans_huge_withdraw
after finishing pmdp related operations.
Cc: Andrea Arcangeli
Signed-off-by: Aneesh Kumar K.V
---
mm/huge_memory.c |3 ++-
1 file chang
From: "Aneesh Kumar K.V"
We allocate one page for the last level of linux page table. With THP and
large page size of 16MB, that would mean we are wasting large part
of that page. To map 16MB area, we only need a PTE space of 2K with 64K
page size. This patch reduce the space wastage by sharing t
From: "Aneesh Kumar K.V"
We now have pmd entries covering to 16MB range. To implement THP on powerpc,
we double the size of PMD. The second half is used to deposit the pgtable (PTE
page).
We also use the depoisted PTE page for tracking the HPTE information. The
information
include [ secondary g
From: "Aneesh Kumar K.V"
We now have pmd entries covering to 16MB range. To implement THP on powerpc,
we double the size of PMD. The second half is used to deposit the pgtable (PTE
page).
We also use the depoisted PTE page for tracking the HPTE information. The
information
include [ secondary g
From: "Aneesh Kumar K.V"
THP code does PTE page allocation along with large page request and deposit them
for later use. This is to ensure that we won't have any failures when we split
hugepages to regular pages.
On powerpc we want to use the deposited PTE page for storing hash pte slot and
seco
From: "Aneesh Kumar K.V"
HUGETLB clear the top bit of PMD entries and use that to indicate
a HUGETLB page directory. Since we store pfns in PMDs for THP,
we would have the top bit cleared by default. Add the top bit mask
for THP PMD entries and clear that when we are looking for pmd_pfn.
Signed-
From: "Aneesh Kumar K.V"
We enable only if the we support 16MB page size.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/pgtable.h | 31 +--
1 file changed, 29 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/include/asm/pgtable.h
b/arch/pow
From: "Aneesh Kumar K.V"
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/perf/callchain.c | 32 +---
1 file changed, 21 insertions(+), 11 deletions(-)
diff --git a/arch/powerpc/perf/callchain.c b/arch/powerpc/perf/callchain.c
index 578cac7..99262ce 100644
--- a/a
From: "Aneesh Kumar K.V"
We could possibly avoid some of these changes because most of the HUGE PMD bits
map to PTE bits.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/kvm_book3s_64.h | 31
arch/powerpc/kvm/book3s_64_mmu_hv.c | 12 -
arch/powerpc/kvm/bo
From: "Aneesh Kumar K.V"
Hugepage invalidate involves invalidating multiple hpte entries.
Optimize the operation using H_BULK_REMOVE on lpar platforms.
On native, reduce the number of tlb flush.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/machdep.h|3 +
arch/powerpc/mm
From: "Aneesh Kumar K.V"
handle large pages for get_user_pages_fast. Also take care of large page
splitting.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/mm/gup.c | 84 +++--
1 file changed, 82 insertions(+), 2 deletions(-)
diff --git a/arch/
Hi Aneesh,
On 04/04/2013 01:57 PM, Aneesh Kumar K.V wrote:
Hi,
This patchset adds transparent hugepage support for PPC64.
TODO:
* hash preload support in update_mmu_cache_pmd (we don't do that for hugetlb)
Some numbers:
The latency measurements code from Anton found at
http://ozlabs.org/~ant
Simon Jeons writes:
> Hi Aneesh,
> On 04/04/2013 01:57 PM, Aneesh Kumar K.V wrote:
>> Hi,
>>
>> This patchset adds transparent hugepage support for PPC64.
>>
>> TODO:
>> * hash preload support in update_mmu_cache_pmd (we don't do that for hugetlb)
>>
>> Some numbers:
>>
>> The latency measurement
Hi Aneesh,
On 04/04/2013 01:57 PM, Aneesh Kumar K.V wrote:
Hi,
This patchset adds transparent hugepage support for PPC64.
TODO:
* hash preload support in update_mmu_cache_pmd (we don't do that for hugetlb)
Some numbers:
The latency measurements code from Anton found at
http://ozlabs.org/~ant
On 3 April 2013 16:00, Benjamin Herrenschmidt wrote:
> On Wed, 2013-04-03 at 15:00 +0530, Viresh Kumar wrote:
>> On 31 March 2013 09:33, Viresh Kumar wrote:
>> > Benjamin/Paul/Olof,
>> >
>> > Any comments on this?
>>
>> Ping!!
>
> I'm on vacation until end of April. No objection to the patch but
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