This patch is present in the "next branch" of linux ppc tree maintained by
Kumar Gala.
Following is the commit id:
52c5affc545053d37c0b05224bbf70f5336caa20
I am not sure if this would be part of 3.9-rc1.
Regards
varun
> -Original Message-
> From: Joerg Roedel [mailto:j...@8bytes.org]
>
On Tue, Feb 26, 2013 at 06:16:10AM +, Sethi Varun-B16395 wrote:
> This patch is not present in Joerg's tree and the add_device API in
> the PAMU driver requires this patch.
Will this patch be part of v3.9-rc1?
Joerg
___
Linuxppc-dev maili
Hi Srivatsa,
I think there is some elegance in Lai's proposal of using a local
trylock for the reader uncontended case and global rwlock to deal with
the contended case without deadlocks. He apparently didn't realize
initially that nested read locks are common, and he seems to have
confused you be
On Mon, Feb 18, 2013 at 06:22:14PM +0530, Varun Sethi wrote:
> Add a new field in the device (powerpc) archdata structure for storing iommu
> domain
> information pointer. This pointer is stored when the device is attached to a
> particular
> domain.
>
>
> Signed-off-by: Varun Sethi
> ---
> -
On Mon, Feb 18, 2013 at 06:22:16PM +0530, Varun Sethi wrote:
> Macros for checking FSL PCI controller version.
>
> Signed-off-by: Varun Sethi
> ---
> arch/powerpc/include/asm/pci-bridge.h |4
> 1 files changed, 4 insertions(+), 0 deletions(-)
>
> diff --git a/arch/powerpc/include/asm/p
On Mon, Feb 18, 2013 at 06:22:18PM +0530, Varun Sethi wrote:
> Added the following domain attributes for the FSL PAMU driver:
> 1. Added new iommu stash attribute, which allows setting of the
>LIODN specific stash id parameter through IOMMU API.
> 2. Added an attribute for enabling/disabling DM
> -Original Message-
> From: Stuart Yoder [mailto:b08...@gmail.com]
> Sent: Wednesday, February 27, 2013 4:03 AM
> To: Sethi Varun-B16395
> Cc: io...@lists.linux-foundation.org; linuxppc-dev@lists.ozlabs.org;
> linux-ker...@vger.kernel.org; Wood Scott-B07421; Joerg Roedel; Yoder
> Stuart-
Hi Kumar,Ben,
I am implementing the Freescale PAMU (IOMMU) driver using the Linux IOMMU API.
In this particular patch, I have added a new field to dev_archdata structure to
store the dma domain information.
This field is updated whenever we attach a device to an iommu domain.
Regards
Varun
> --
On 02/27, Michel Lespinasse wrote:
>
> +void lg_rwlock_local_read_lock(struct lgrwlock *lgrw)
> +{
> + preempt_disable();
> +
> + if (__this_cpu_read(*lgrw->local_refcnt) ||
> + arch_spin_trylock(this_cpu_ptr(lgrw->lglock->lock))) {
> + __this_cpu_inc(*lgrw->loca
Hi Christophe,
> This patch modifies the behaviour of the MPC8xx/8xxx watchdog. On the MPC8xx,
> at 133Mhz, the maximum timeout of the watchdog timer is 1s, which means it
> must
> be pinged twice a second. This is not in line with the Linux watchdog concept
> which is based on a default watchdog
Currently we use the link register to branch up high in the early MMU on
syscall entry path. Unfortunately, this trashes the link stack as the
address we are going to is not associated with the earlier mflr.
This patch simply converts us to used the count register (volatile over
syscalls anyway)
On 02/27/2013 06:03 AM, Lai Jiangshan wrote:
> On Wed, Feb 27, 2013 at 3:30 AM, Srivatsa S. Bhat
> wrote:
>> On 02/26/2013 09:55 PM, Lai Jiangshan wrote:
>>> On Tue, Feb 26, 2013 at 10:22 PM, Srivatsa S. Bhat
>>> wrote:
Hi Lai,
I'm really not convinced that piggy-backing on lg
Some more comments...
On Mon, Feb 18, 2013 at 6:52 AM, Varun Sethi wrote:
> +/* Handling access violations */
> +#define make64(high, low) (((u64)(high) << 32) | (low))
> +
> +struct pamu_isr_data {
> + void __iomem *pamu_reg_base;/* Base address of PAMU regs*/
> + unsigned int co
On Tue, Feb 26, 2013 at 01:34:53PM +0530, Aneesh Kumar K.V wrote:
> From: "Aneesh Kumar K.V"
>
> USE PTRS_PER_PTE to indicate the size of pte page. To support THP,
> later patches will be changing PTRS_PER_PTE value.
>
> Signed-off-by: Aneesh Kumar K.V
Acked-by: Paul Mackerras
___
14 matches
Mail list logo
