From: "Aneesh Kumar K.V"
VSID_BITS and VSID_BITS_1T depends on the context bits and user esid
bits. Make the dependency explicit
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/mmu-hash64.h | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/arch/pow
From: "Aneesh Kumar K.V"
This patch change the kernel VSID range so that we limit VSID_BITS to 37.
This enables us to support 64TB with 65 bit VA (37+28). Without this patch
we have boot hangs on platforms that only support 65 bit VA.
With this patch we now have proto vsid generated as below:
W
From: "Aneesh Kumar K.V"
We need to make sure that we don't have higher bits of kernel effective
address set. That would result in multiple kernel segments having same
proto vsid. Add debug code to make sure we capture this.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/mmu-hash
From: "Aneesh Kumar K.V"
This enables us to use r10 as scratch in the code.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/mm/slb_low.S |8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/mm/slb_low.S b/arch/powerpc/mm/slb_low.S
index 487f998..2a233cb
From: Diana Craciun
On Freescale e6500 cores EPCR[DGTMI] controls whether guest supervisor
state can execute TLB management instructions. If EPCR[DGTMI]=0
tlbwe and tlbilx are allowed to execute normally in the guest state.
A hypervisor may choose to virtualize TLB1 and for this purpose it
may u
"Aneesh Kumar K.V" writes:
> From: "Aneesh Kumar K.V"
>
> This patch change the kernel VSID range so that we limit VSID_BITS to 37.
> This enables us to support 64TB with 65 bit VA (37+28). Without this patch
> we have boot hangs on platforms that only support 65 bit VA.
>
> With this patch we n
On Thu, 2013-02-14 at 14:56 +0200, Diana Craciun wrote:
> From: Diana Craciun
>
> On Freescale e6500 cores EPCR[DGTMI] controls whether guest supervisor
> state can execute TLB management instructions. If EPCR[DGTMI]=0
> tlbwe and tlbilx are allowed to execute normally in the guest state.
>
> A
Currently ptrace_get_reg returns error as a value
what make impossible to tell whether it is a correct value or error code.
The patch adds a parameter which points to the real return data and
returns an error code.
As get_user_msr() never fails and it is used in multiple places so it has not
been
On Mon, Feb 11, 2013 at 11:12:40PM +1100, a...@ozlabs.ru wrote:
> From: Alexey Kardashevskiy
>
> The lookup_linux_pte() function returns a linux PTE which
> is required to convert KVM guest physical address into host real
> address in real mode.
>
> This convertion will be used by upcoming suppo
On Mon, Feb 11, 2013 at 11:12:42PM +1100, a...@ozlabs.ru wrote:
> From: Alexey Kardashevskiy
>
> he current VFIO-on-POWER implementation supports only user mode
> driven mapping, i.e. QEMU is sending requests to map/unmap pages.
> However this approach is really slow in really fast hardware so
>
On Mon, Feb 11, 2013 at 11:12:43PM +1100, a...@ozlabs.ru wrote:
> From: Alexey Kardashevskiy
>
> The patch allows the host kernel to handle H_PUT_TCE request
> without involving QEMU in it what should save time on switching
> from the kernel to QEMU and back.
>
> The patch adds an IOMMU ID param
On Mon, Feb 11, 2013 at 11:12:41PM +1100, a...@ozlabs.ru wrote:
> +static long emulated_h_put_tce(struct kvmppc_spapr_tce_table *stt,
> + unsigned long ioba, unsigned long tce)
> +{
> + unsigned long idx = ioba >> SPAPR_TCE_SHIFT;
> + struct page *page;
> + u64 *tbl;
> +
>
On Thu, Feb 14, 2013 at 02:06:21PM +0530, Aneesh Kumar K.V wrote:
> From: "Aneesh Kumar K.V"
>
> This patch change the kernel VSID range so that we limit VSID_BITS to 37.
> This enables us to support 64TB with 65 bit VA (37+28). Without this patch
> we have boot hangs on platforms that only suppo
On Thu, Feb 14, 2013 at 02:06:23PM +0530, Aneesh Kumar K.V wrote:
> From: "Aneesh Kumar K.V"
>
> We need to make sure that we don't have higher bits of kernel effective
> address set. That would result in multiple kernel segments having same
> proto vsid. Add debug code to make sure we capture th
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