On Fri, Nov 09, 2012 at 05:18:58PM +1100, Michael Neuling wrote:
> This set of patches adds support for taking exceptions with the MMU on which
> is
> supported by POWER8.
>
> A new set of exception vectors is added at 0xc000___4xxx. When the HW
> takes us here, MSR IR/DR will be set alr
On Fri, Nov 09, 2012 at 05:26:42PM +1100, Michael Neuling wrote:
> A PVR of 0x0F04 means we are arch v2.07 complicate ie, POWER8.
Huh?
s/complicate/compliant/ ?
Also ie has to be written with dots (i.e.).
Gabriel
>
> Signed-off-by: Michael Neuling
>
> diff --git a/arch/powe
Hi Mikey,
On Fri, 9 Nov 2012 17:19:11 +1100 Michael Neuling wrote:
>
> From: Ian Munsie
>
> I am going to use this in the next patch, better to have this code in
> one place rather than three.
>
> Signed-off-by: Ian Munsie
> Signed-off-by: Michael Neuling
> ---
> arch/powerpc/include/asm/h
Stephen Rothwell wrote:
> Hi Mikey,
>
> On Fri, 9 Nov 2012 17:19:11 +1100 Michael Neuling wrote:
> >
> > From: Ian Munsie
> >
> > I am going to use this in the next patch, better to have this code in
> > one place rather than three.
> >
> > Signed-off-by: Ian Munsie
> > Signed-off-by: Mich
> > This set of patches adds support for taking exceptions with the MMU on
> > which is
> > supported by POWER8.
> >
> > A new set of exception vectors is added at 0xc000___4xxx. When the
> > HW
> > takes us here, MSR IR/DR will be set already and we no longer need a costly
> > RFID to
> On Fri, Nov 09, 2012 at 05:26:42PM +1100, Michael Neuling wrote:
> > A PVR of 0x0F04 means we are arch v2.07 complicate ie, POWER8.
>
> Huh?
>
> s/complicate/compliant/ ?
Yes, compliant. Thanks
> Also ie has to be written with dots (i.e.).
Thanks.
Mikey
___
On Thu, Nov 8, 2012 at 2:10 AM, Sukadev Bhattiprolu
wrote:
>
>
> Looking for feedback on this prototype for making POWER-specific event
> translations available in sysfs. It is based on the patchset:
>
> https://lkml.org/lkml/2012/11/7/402
>
> which makes the translations for _generic_ eve
The CPU_FTR_* values are pretty tight (a few bits left) yes I need to save and
restore the QPX registers.
There are 32 QPX registers, each 32 bytes in size, it is otherwise managed by
the FPSCR and MSR[FP]
I was thinking that I could hijack the VSX, since there is no plan to add it to
embedded
On Fri, 2012-11-09 at 11:43 -0600, Jimi Xenidis wrote:
> The CPU_FTR_* values are pretty tight (a few bits left) yes I need to save
> and restore the QPX registers.
> There are 32 QPX registers, each 32 bytes in size, it is otherwise managed by
> the FPSCR and MSR[FP]
>
> I was thinking that I c
Benjamin Herrenschmidt wrote:
> On Fri, 2012-11-09 at 11:43 -0600, Jimi Xenidis wrote:
> > The CPU_FTR_* values are pretty tight (a few bits left) yes I need to save
> > and restore the QPX registers.
> > There are 32 QPX registers, each 32 bytes in size, it is otherwise managed
> > by the FPSC
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