Ensure the Chelsio T3/T4 network drivers and iWARP drivers are
enabled in the pseries config.
Signed-off-by: Anton Blanchard
---
Index: linux-2.6/arch/powerpc/configs/pseries_defconfig
===
--- linux-2.6.orig/arch/powerpc/configs/ps
From: Kumar Gala
If the spin table is located in the linear mapping (which can happen if
we have 4G or more of memory) we need to access the spin table via a
cacheable coherent mapping like we do on ppc32 (and do explicit cache
flush).
See the following commit for the ppc32 version of this issue
On Feb 24, 2011, at 3:35 AM, Prabhakar Kushwaha wrote:
> FSL PCIe controller v2.1:
> - New MSI inbound window
> - Same Inbound windows address as PCIe controller v1.x
>
> Added new pit_t member(pmit) to struct ccsr_pci for MSI inbound window
>
> FSL PCIe controller v2.2 and v2.3:
>