For FSL PPC SoCs USB_ARCH_HAS_EHCI currently on depends on PPC_83xx.
However that excludes support for USB on 85xx & QorIQ devices. Use
FSL_SOC insted which will get us 83xx, 85xx, QorIQ, and 5xxx which all
have the same USB IP on them.
Signed-off-by: Xulei
Signed-off-by: Kumar Gala
---
driver
On 01/08/2011 06:07 AM, Gary Thomas wrote:
On 01/08/2011 12:33 AM, Benjamin Herrenschmidt wrote:
On Fri, 2011-01-07 at 16:06 -0700, Gary Thomas wrote:
I just tried porting my target (MPC8347) from 2.6.28 (remember
that one?) to 2.6.37. Recently I tried this with 2.6.32 without
a lot of success,
On Jan 10, 2011, at 4:06 AM, Xulei wrote:
> For FSL PPC SoCs USB_ARCH_HAS_EHCI currently on depends on PPC_83xx.
> However that excludes support for USB on 85xx & QorIQ devices. Use
> FSL_SOC insted which will get us 83xx, 85xx, QorIQ, and 5xxx which all
> have the same USB IP on them.
>
> Sign
>
> Once you have tested it and it works, please send a patch to remove the 8xx
> workaround.
> Make sure Scott is cc:ed
>
>
I tested linux-2.6.33 on my ppc880 board today, and even without the
slowdown.patch applied, the board runs processes with good
performance.
It really seems that the proble
Rafael Beims wrote on 2011/01/10 17:35:38:
> >
> > Once you have tested it and it works, please send a patch to remove the 8xx
> > workaround.
> > Make sure Scott is cc:ed
> >
> >
>
> I tested linux-2.6.33 on my ppc880 board today, and even without the
> slowdown.patch applied, the board runs pro
This is a re-send of the remaining patches that did not make it
into the last kernel release for de-coupling sysfs memory
directories from memory sections. The first three patches of the
previous set went in, and this is the remaining patches that
need to be applied.
The patches decouple the conc
Update the memory sysfs code such that each sysfs memory directory is now
considered a memory block that can span multiple memory sections per
memory block. The default size of each memory block is SECTION_SIZE_BITS
to maintain the current behavior of having a single memory section per
memory bloc
Update the 'phys_index' property of a the memory_block struct to be
called start_section_nr, and add a end_section_nr property. The
data tracked here is the same but the updated naming is more in line
with what is stored here, namely the first and last section number
that the memory block spans.
Define a version of memory_block_size_bytes() for powerpc/pseries such that
a memory block spans an entire lmb.
Signed-off-by: Nathan Fontenot
Reviewed-by: Robin Holt
---
arch/powerpc/platforms/pseries/hotplug-memory.c | 66 +++-
1 file changed, 53 insertions(+), 13 delet
Define a version of memory_block_size_bytes for x86_64 when CONFIG_X86_UV is
set.
Signed-off-by: Robin Holt
Signed-off-by: Jack Steiner
Signed-off-by: Nathan Fontenot
---
arch/x86/mm/init_64.c | 14 ++
1 file changed, 14 insertions(+)
Index: linux-2.6/arch/x86/mm/init_64.c
On Mon, Jan 10, 2011 at 12:08:56PM -0600, Nathan Fontenot wrote:
> This is a re-send of the remaining patches that did not make it
> into the last kernel release for de-coupling sysfs memory
> directories from memory sections. The first three patches of the
> previous set went in, and this is the
On 01/10/2011 12:44 PM, Greg KH wrote:
> On Mon, Jan 10, 2011 at 12:08:56PM -0600, Nathan Fontenot wrote:
>> This is a re-send of the remaining patches that did not make it
>> into the last kernel release for de-coupling sysfs memory
>> directories from memory sections. The first three patches of
> >> The root of this issue is in sysfs directory creation. Every time
> >> a directory is created a string compare is done against all sibling
> >> directories to ensure we do not create duplicates. The list of
> >> directory nodes in sysfs is kept as an unsorted list which results
> >> in this b
This is a backport from 2.6 which I did to overcome 8xx CPU
bugs. 8xx does not update the DAR register when taking a TLB
error caused by dcbX and icbi insns which makes it very
tricky to use these insns. Also the dcbst wrongly sets the
the store bit when faulting into DTLB error.
A few more bugs ve
Signed-off-by: Joakim Tjernlund
---
arch/ppc/kernel/head_8xx.S | 84 +++
1 files changed, 22 insertions(+), 62 deletions(-)
diff --git a/arch/ppc/kernel/head_8xx.S b/arch/ppc/kernel/head_8xx.S
index f9a30f3..ba05a57 100644
--- a/arch/ppc/kernel/head_8xx
dcbz, dcbf, dcbi, dcbst and icbi do not set DAR when they
cause a DTLB Error. Dectect this by tagging DAR with 0x00f0
at every exception exit that modifies DAR.
This also fixes MachineCheck to pass DAR and DSISR as well.
Signed-off-by: Joakim Tjernlund
---
arch/ppc/kernel/head_8xx.S | 18 +
8xx sometimes need to load a invalid/non-present TLBs in
it DTLB asm handler.
These must be invalidated separaly as linux mm don't.
Signed-off-by: Joakim Tjernlund
---
arch/ppc/mm/fault.c |8 +++-
1 files changed, 7 insertions(+), 1 deletions(-)
diff --git a/arch/ppc/mm/fault.c b/arch/p
The wrong register was loaded into MD_RPN.
Signed-off-by: Joakim Tjernlund
---
arch/ppc/kernel/head_8xx.S |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/ppc/kernel/head_8xx.S b/arch/ppc/kernel/head_8xx.S
index 57858ce..5269e5b 100644
--- a/arch/ppc/kernel/head_8
Update the TLB asm to make proper use of _PAGE_DIRTY and _PAGE_ACCESSED.
Get rid of _PAGE_HWWRITE too.
Pros:
- PRESENT is copied to ACCESSED, fixing accounting
- DIRTY is mapped to 0x100, the changed bit, and is set directly
when a page has been made dirty.
- Proper RO/RW mapping of user
Various kernel asm modifies SRR0/SRR1 just before executing
a rfi. If such code crosses a page boundary you risk a TLB miss
which will clobber SRR0/SRR1. Avoid this by always pinning
kernel instruction TLB space.
Signed-off-by: Joakim Tjernlund
---
arch/ppc/kernel/head_8xx.S |9 +
1
This is an assembler version to fixup DAR not being set
by dcbX, icbi instructions. There are two versions, one
uses selfmodifing code, the other uses a
jump table but is much bigger(default).
Signed-off-by: Joakim Tjernlund
---
arch/ppc/kernel/head_8xx.S | 149 +
branch to common code in DTLB Miss instead.
Signed-off-by: Joakim Tjernlund
---
arch/ppc/kernel/head_8xx.S | 23 ++-
1 files changed, 2 insertions(+), 21 deletions(-)
diff --git a/arch/ppc/kernel/head_8xx.S b/arch/ppc/kernel/head_8xx.S
index 52ff914..0aab8ca 100644
--- a/a
only DTLB Miss did set this bit, DTLB Error needs too otherwise
the setting is lost when the page becomes dirty.
Signed-off-by: Joakim Tjernlund
---
arch/ppc/kernel/head_8xx.S | 12 +---
1 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/arch/ppc/kernel/head_8xx.S b/arch/pp
8xx has not had WRITETHRU due to lack of bits in the pte.
After the recent rewrite of the 8xx TLB code, there are
two bits left. Use one of them to WRITETHRU.
Signed-off-by: Joakim Tjernlund
---
arch/ppc/kernel/head_8xx.S |8
include/asm-ppc/pgtable.h |5 +++--
2 files changed,
Now that 8xx can fixup dcbX instructions, start using them
where possible like every other PowerPc arch do.
Signed-off-by: Joakim Tjernlund
---
arch/ppc/kernel/misc.S | 18 --
arch/ppc/lib/string.S | 17 -
2 files changed, 0 insertions(+), 35 deletions(-)
di
Don't check for kernel space if no modules.
Signed-off-by: Joakim Tjernlund
---
arch/ppc/kernel/head_8xx.S |5 +
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/arch/ppc/kernel/head_8xx.S b/arch/ppc/kernel/head_8xx.S
index 43bccb1..5dbbdb4 100644
--- a/arch/ppc/kernel/head
Only update pte w.r.t ACCESSED if it isn't already set
Signed-off-by: Joakim Tjernlund
---
arch/ppc/kernel/head_8xx.S |7 +++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/arch/ppc/kernel/head_8xx.S b/arch/ppc/kernel/head_8xx.S
index 5dbbdb4..75acaa0 100644
--- a/arch/pp
Previously a check was done on an ID register at the base of a CPU's
internal USB registers to determine if system interface regsiters were
present. The check looked for an ID register that had the format
ID[0:5] == ~ID[8:13] as described in the MPC5121 User's Manual to
determine if a MPC5121 or M
> I found the problem - a change I had in <2.6.32 that I hadn't
> pushed forward. It seems to be related to how I have the PCI
> controller setup (in RedBoot). Because of this, using these
> settings in my DTS make things work properly:
> ranges = <0x0200 0x0 0x 0xC000 0x0 0
Hi Joakim,
On Mon, Jan 10, 2011 at 10:37:46PM +0100, Joakim Tjernlund wrote:
> This is a backport from 2.6 which I did to overcome 8xx CPU
> bugs. 8xx does not update the DAR register when taking a TLB
> error caused by dcbX and icbi insns which makes it very
> tricky to use these insns. Also the
30 matches
Mail list logo
