Ganesh Kumar wrote on 03/09/2009 06:45:14:
>
> Hi Tjernlund,
>
> Thanks a lot for the reply.
>
> I checked in my code regarding to the invalidate/flushing of the
> data cache. In the fec_init its been done by calling the sequence
>
>/* Make it uncached.
> */
> pte = va_
Hi Adam,
If you have a look in include/asm-ppc/pgtable.h for the following section:
#ifdef CONFIG_44x
#define _PAGE_BASE(_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_GUARDED)
#else
#define _PAGE_BASE(_PAGE_PRESENT | _PAGE_ACCESSED)
#endif
Try adding _PAGE_COHERENT to the appropriate line above
Dear All,
Currently we are using the MPC8360E processor, for that we face the problem
with Ethernet port (UCC) port, which one configures as RMII mode. We get the
error like "NETDEV WATCHDOG: eth2 tx transmit timeout", When applied more
load on port. Can u give me any solution for this problem; I
On Thu, 2009-09-03 at 10:12 +0530, Arun R Bharadwaj wrote:
> > OK, that's a start I guess. Best would be to replace all of pm_idle with
> > cpuidle, which is what should have been done from the very start.
> >
> > If cpuidle cannot fully replace the pm_idle functionality, then it needs
> > to fix
On Thu, 2009-09-03 at 09:05 +0100, Chris Pringle wrote:
> Hi Adam,
>
> If you have a look in include/asm-ppc/pgtable.h for the following section:
> #ifdef CONFIG_44x
> #define _PAGE_BASE(_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_GUARDED)
> #else
> #define _PAGE_BASE(_PAGE_PRESENT | _PAGE_ACCE
On Wed, 2009-09-02 at 16:44 -0700, Eddie Dawydiuk wrote:
> Hello,
>
> I have a question regarding reading PCI bus registers from a user space
> application running on a PPC SBC. Seeing as though the PCI bus is little
> endian
> and PPC is big endian is it typical that one must perform a byte sw
In our case, we were suffering coherency issues on an 8260 when using
DMA with PCI. Setting the 'M' bit cured all of our DMA coherency issues.
There is a comment in "pgtable-ppc32.h" on 2.6.29.6 that says:
"We always set _PAGE_COHERENT when SMP is enabled *or* the processor
might need it for DM
Benjamin Gamsa wrote:
Benjamin Herrenschmidt wrote:
On Mon, 2009-08-31 at 23:57 -0400, Benjamin Gamsa wrote:
Sean MacLennan wrote:
On Mon, 31 Aug 2009 22:20:00 -0400
Benjamin Gamsa wrote:
For what it's worth, the problem occurs even when ntp is not even
started.
This is grasping, but could
Hi,
This doesn't seem right. If we are talking about a single CPU core chip,
i.e., just one data cache, then setting M is typically a) useless and
could even b) cause a performance penalty depending on a chip's
implementation.
The M bit is required if *other* cores with caches need to see changes
With benh's test branch, I'm seeing this trying to build a 6xx defconfig
with CONFIG_PPC_PERF_CTRS=y:
arch/powerpc/kernel/perf_counter.c: In function 'power_check_constraints':
arch/powerpc/kernel/perf_counter.c:352: error: the frame size of 1152 bytes is
larger than 1024 bytes
cheers
signatur
Hi,
This is the same patch but with a signed-off message which I forgot.
Regards,
Roderick Colenbrander
Signed-off-by: Roderick Colenbrander
>From 11a2072b285c2eb0f19980ad729229d4ebf22291 Mon Sep 17 00:00:00 2001
From: Roderick Colenbrander
Date: Thu, 3 Sep 2009 15:11:08 +0200
Subject: [PATCH
>From 11a2072b285c2eb0f19980ad729229d4ebf22291 Mon Sep 17 00:00:00 2001
From: Roderick Colenbrander
Date: Thu, 3 Sep 2009 15:11:08 +0200
Subject: [PATCH] This patch fixes a null pointer exception caused by
removal of 'ack()' for level interrupts in the Xilinx interrupt driver.
---
arch/powerpc/s
From: Roderick Colenbrander
This patch fixes a null pointer exception caused by removal of
'ack()' for level interrupts in the Xilinx interrupt driver. A recent
change to the xilinx interrupt controller removed the ack hook for
level irqs.
Signed-off-by: Roderick Colenbrander
Signed-off-by: Gr
Chris,
I noticed the following comment in pgtable.h:
* - CACHE COHERENT bit (M) has no effect on PPC440 core, because it
* doesn't support SMP. So we can use this as software bit, like
* DIRTY.
And _PAGE_COHERENT is not defined for the 44x (giving a compile error
when I add it the _PA
Ben,
Thanks for your info.
Are you sure there is L2 cache on the 440?
I am seeing this problem with our custom IDE driver which is based on
pretty old code. Our driver uses pci_alloc_consistent() to allocate the
physical DMA memory and alloc_pages() to allocate a virtual page. It
then uses pci_m
On Thu, Sep 03, 2009 at 12:04:50PM -0400, Adam Zilkie wrote:
>Ben,
>
>Thanks for your info.
>
>Are you sure there is L2 cache on the 440?
It depends on which 440 SoC you have. It also depends on that being
configured in the kernel even if it does exist.
>I am seeing this problem with our custom
On Wed, Sep 2, 2009 at 5:04 AM, Sebastian Andrzej
Siewior wrote:
> Usually u-boot sends a phy request in its network init routine. An uboot
> without network support doesn't do it and I endup without working
> network. I still can switch between 10/100Mbit (according to the LED on
> the hub and phy
Hi All,
Please find a new set of patches with the changes as listed below.
These patches have to be applied over the set of patches sent to LKML here:
http://lkml.org/lkml/2009/8/28/272 that enable per-cpu breakpoint support and
a few new APIs.
Changelog - ver IX
---
- Inv
Prepare the PowerPC code for HW Breakpoint infrastructure patches by including
relevant constant definitions and function declarations.
Signed-off-by: K.Prasad
---
arch/powerpc/include/asm/hw_breakpoint.h | 61 +++
arch/powerpc/include/asm/processor.h |1
a
Introduce PPC64 implementation for the generic hardware breakpoint interfaces
defined in kernel/hw_breakpoint.c. Enable the HAVE_HW_BREAKPOINT flag and the
Makefile.
Signed-off-by: K.Prasad
---
arch/powerpc/Kconfig|1
arch/powerpc/kernel/Makefile|2
arch/powerpc
Modify the ptrace code to use the hardware breakpoint interfaces for user-space.
Signed-off-by: K.Prasad
---
arch/powerpc/kernel/ptrace.c | 43 +++
1 file changed, 43 insertions(+)
Index: linux-2.6-tip.hbkpt/arch/powerpc/kernel/ptrace.c
Modify process handling code to recognise hardware debug registers during copy
and flush operations. Introduce a new TIF_DEBUG task flag to indicate a
process's use of debug register. Load the debug register values into a
new CPU during initialisation.
Signed-off-by: K.Prasad
---
arch/powerpc/ke
Modify Data storage exception code to first lookout for a DABR match before
recognising a kprobe or xmon exception.
Signed-off-by: K.Prasad
---
arch/powerpc/mm/fault.c | 14 ++
1 file changed, 6 insertions(+), 8 deletions(-)
Index: linux-2.6-tip.hbkpt/arch/powerpc/mm/fault.c
=
Modify kexec code to disable DABR registers before a reboot. Adapt the samples
code to populate PPC64-arch specific fields.
Signed-off-by: K.Prasad
---
arch/powerpc/kernel/machine_kexec_64.c |3 +++
samples/hw_breakpoint/data_breakpoint.c |4
2 files changed, 7 insertions(+)
Index
Hi Adam,
> Are you sure there is L2 cache on the 440?
It depends on the SoC you are using. SoC like 460EX (Canyonlands board)
have L2Cache.
It seems you are using a Sequoia board, which has a 440EPx SoC. 440EPx
has a 440 cpu core, but no L2Cache.
Could you please tell me which SoC you are using?
On Thu, 2009-09-03 at 09:57 -0600, Grant Likely wrote:
> From: Roderick Colenbrander
>
> This patch fixes a null pointer exception caused by removal of
> 'ack()' for level interrupts in the Xilinx interrupt driver. A recent
> change to the xilinx interrupt controller removed the ack hook for
> l
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