On Wed, Jul 13, 2016 at 03:05:21PM +0530, Aneesh Kumar K.V wrote:
> PowerISA 3.0 requires the MMU mode (radix vs. hash) of the hypervisor
> to be mirrored in the LPCR register, in addition to the partition table.
> This is done to avoid fetching from the table when deciding, among other
> things, h
PowerISA 3.0 requires the MMU mode (radix vs. hash) of the hypervisor
to be mirrored in the LPCR register, in addition to the partition table.
This is done to avoid fetching from the table when deciding, among other
things, how to perform transitions to HV mode on some interrupts.
So let's set it u
PowerISA 3.0 requires the MMU mode (radix vs. hash) of the hypervisor
to be mirrored in the LPCR register, in addition to the partition table.
This is done to avoid fetching from the table when deciding, among other
things, how to perform transitions to HV mode on some interrupts.
So let's set it u
On Thu, 2016-02-06 at 09:40:57 UTC, "Aneesh Kumar K.V" wrote:
> We need to se HR bit LPCR for radix partitions.
Please update the change log with something similar to what Ben sent.
> Signed-off-by: Aneesh Kumar K.V
> ---
> arch/powerpc/include/asm/reg.h | 1 +
> arch/powerpc/mm/pgtable-radix
On Thu, 2016-06-02 at 15:10 +0530, Aneesh Kumar K.V wrote:
> We need to se HR bit LPCR for radix partitions.
Again (:-) please a better changeset description. In fact this
one is actually incorrect, this is not a partition.
Something like "The processor requires the MMU mode (radix vs. ha
We need to se HR bit LPCR for radix partitions.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/reg.h | 1 +
arch/powerpc/mm/pgtable-radix.c | 4 ++--
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
inde
