Felix Radensky wrote:
Are you aware of Freescale plans to fix the problem in new silicon
revisions ?
I don't know anything yet -- still trying to get in touch with the
relevant hardware people.
Also, can you please tell what CPUs are affected by this, except 8536
and 8572.
I suppose anyth
Hi, Scott
Scott Wood wrote:
On Fri, Oct 16, 2009 at 07:01:43AM +0200, Felix Radensky wrote:
Thanks for confirmation. So the real problem is eLBC ?
What happens if I access other devices on eLBC (e.g. FPGA)
simultaneously with NAND or NOR ?
AFAICT, the problem is NAND being accessed si
Scott Wood wrote:
Felix Radensky wrote:
OK, no problem. I just wanted to get an idea of what should be done.
Should the NOR code poll some eLBC register to wait for completion of
NAND special operation ? Can you tell what register is relevant ?
I was thinking you'd just share a mutex with the
Scott Wood wrote:
Felix Radensky wrote:
OK, no problem. I just wanted to get an idea of what should be done.
Should the NOR code poll some eLBC register to wait for completion of
NAND special operation ? Can you tell what register is relevant ?
I was thinking you'd just share a mutex with the
Felix Radensky wrote:
OK, no problem. I just wanted to get an idea of what should be done.
Should the NOR code poll some eLBC register to wait for completion of
NAND special operation ? Can you tell what register is relevant ?
I was thinking you'd just share a mutex with the NAND code.
-Scott
Scott Wood wrote:
On Sun, Oct 18, 2009 at 11:38:13AM +0200, Felix Radensky wrote:
Hi, Scott
Scott Wood wrote:
On Fri, Oct 16, 2009 at 07:01:43AM +0200, Felix Radensky wrote:
Thanks for confirmation. So the real problem is eLBC ?
What happens if I access other devices on eLBC (e
On Sun, Oct 18, 2009 at 11:38:13AM +0200, Felix Radensky wrote:
> Hi, Scott
>
> Scott Wood wrote:
>> On Fri, Oct 16, 2009 at 07:01:43AM +0200, Felix Radensky wrote:
>>> Thanks for confirmation. So the real problem is eLBC ?
>>> What happens if I access other devices on eLBC (e.g. FPGA)
>>> simultan
Hi, Scott
Scott Wood wrote:
On Fri, Oct 16, 2009 at 07:01:43AM +0200, Felix Radensky wrote:
Thanks for confirmation. So the real problem is eLBC ?
What happens if I access other devices on eLBC (e.g. FPGA)
simultaneously with NAND or NOR ?
AFAICT, the problem is NAND being accessed simultaneo
On Fri, Oct 16, 2009 at 07:01:43AM +0200, Felix Radensky wrote:
> Thanks for confirmation. So the real problem is eLBC ?
> What happens if I access other devices on eLBC (e.g. FPGA)
> simultaneously with NAND or NOR ?
AFAICT, the problem is NAND being accessed simultaneously with anything else
on
Hi, Scott
Scott Wood wrote:
Scott Wood wrote:
Felix Radensky wrote:
Yes, NAND and NOR are on the same local bus controller.
Maybe powerpc folks can provide some insight here.
Is it possible that simultaneous access to NOR and NAND
on MPC8536 can result in NAND timeouts ?
I've heard other re
Scott Wood wrote:
Felix Radensky wrote:
Yes, NAND and NOR are on the same local bus controller.
Maybe powerpc folks can provide some insight here.
Is it possible that simultaneous access to NOR and NAND
on MPC8536 can result in NAND timeouts ?
I've heard other reports of such problems with eL
Hi, Norbert
Norbert van Bolhuis wrote:
Hi Felix,
do you have CONFIG_NO_HZ defined ?
I've seen similar problems with powerpc + CONFIG_NO_HZ. In my case the
low-level
do_write_buffer (cfi_cmdset_0002.c) timed out too early. See
http://lkml.org/lkml/2009/9/3/84
Maybe in your case it's the do_e
Hi Felix,
do you have CONFIG_NO_HZ defined ?
I've seen similar problems with powerpc + CONFIG_NO_HZ. In my case the low-level
do_write_buffer (cfi_cmdset_0002.c) timed out too early. See
http://lkml.org/lkml/2009/9/3/84
Maybe in your case it's the do_erase_chip timing out too early.
---
NvBolh
Hi, Scott
Scott Wood wrote:
Felix Radensky wrote:
Yes, NAND and NOR are on the same local bus controller.
Maybe powerpc folks can provide some insight here.
Is it possible that simultaneous access to NOR and NAND
on MPC8536 can result in NAND timeouts ?
I've heard other reports of such probl
Felix Radensky wrote:
Yes, NAND and NOR are on the same local bus controller.
Maybe powerpc folks can provide some insight here.
Is it possible that simultaneous access to NOR and NAND
on MPC8536 can result in NAND timeouts ?
I've heard other reports of such problems with eLBC, but was unable
Adrian Hunter wrote:
Felix Radensky wrote:
Adrian Hunter wrote:
Felix Radensky wrote:
Hi,
I have a strange problem in linux-2.6.31 running on MPC8536DS board.
It is 100% reproducible, by opening a 350MB tar file into ubifs volume
on NAND flash, and starting erase of NOR flash partition righ
Felix Radensky wrote:
Adrian Hunter wrote:
Felix Radensky wrote:
Hi,
I have a strange problem in linux-2.6.31 running on MPC8536DS board.
It is 100% reproducible, by opening a 350MB tar file into ubifs volume
on NAND flash, and starting erase of NOR flash partition right after
that.
If I do
Felix Radensky wrote:
Hi,
I have a strange problem in linux-2.6.31 running on MPC8536DS board.
It is 100% reproducible, by opening a 350MB tar file into ubifs volume
on NAND flash, and starting erase of NOR flash partition right after that.
If I don't start NOR erase, everything works fine. Al
Adrian Hunter wrote:
Felix Radensky wrote:
Hi,
I have a strange problem in linux-2.6.31 running on MPC8536DS board.
It is 100% reproducible, by opening a 350MB tar file into ubifs volume
on NAND flash, and starting erase of NOR flash partition right after
that.
If I don't start NOR erase, e
Hi, Adrian
Adrian Hunter wrote:
Felix Radensky wrote:
Hi,
I have a strange problem in linux-2.6.31 running on MPC8536DS board.
It is 100% reproducible, by opening a 350MB tar file into ubifs volume
on NAND flash, and starting erase of NOR flash partition right after
that.
If I don't start
Hi,
I have a strange problem in linux-2.6.31 running on MPC8536DS board.
It is 100% reproducible, by opening a 350MB tar file into ubifs volume
on NAND flash, and starting erase of NOR flash partition right after that.
If I don't start NOR erase, everything works fine. Also, If I run sync
afte
21 matches
Mail list logo
