On Thu, 2012-12-13 at 00:48 -0800, pegasus wrote:
> 1. Linux page table structure (PGD, PUD, PMD and PTE) is directly used in
> case of architecture that lend themselves to such a tree structure for
> maintaining virtual memory information. Otherwise Linux needs to maintain
> two seperate construc
Hi Ben
There has been quite much confusion with my post disappearing from the new
nabble system to it having getting posted twice..Im sorry for all this.
Nevertheless, Id like to continue where we left off. Here I again repost my
response which initially disappeared and then showed up twice. Ive
I cannot see my post at all on the old nabble system...this is just for
testing purposes//...
My last post is fine..but I cannot see my thread on linuxppc-dev@oldnabble
...?? :confused:
--
View this message in context:
http://old.nabble.com/Understanding-how-kernel-updates-MMU-hash-table-tp3476
Hi ben
Now that many things are becoming clear let me sum up my understanding until
this point. Do correct it if there are mistakes.
1. Linux page table structure (PGD, PUD, PMD and PTE) is directly used in
case of architecture that lend themselves to such a tree structure for
maintaining virtua
On Sat, 2012-12-08 at 23:18 -0800, Pegasus11 wrote:
> 3. For 64bit architecture there is no such 'segment register we use a
> segment table entry (STE) from within an SLB (segment lookaside buffer)
> which caches recently used mappings from ESID (part of effective address) to
> VSID (part of Virtua
Hi Ben.
Firstly thanks a lot for being so succint and patient in explaining these
things to me. It helped me guide my way through an assortment of documents
and things are slowly becoming clear. So summing it all up, what I have
understood is this (pls correct me if I am wrong anywhere):
1. The pa
On Wed, 2012-12-05 at 23:57 -0800, Pegasus11 wrote:
> Hi Ben.
>
> Got it..no more quoting replies...
Quoting is fine ... as long as you quote the bits your reply to, not
your actual reply part :)
> You mentioned the MMU looking into a hash table if it misses a translation
> entry in the TLB. Thi
Hi Ben.
Got it..no more quoting replies...
You mentioned the MMU looking into a hash table if it misses a translation
entry in the TLB. This means that there is a hardware TLB for sure. By your
words, I understand that the hash table is an in-memory cache of
translations meaning it is implemente
On Wed, 2012-12-05 at 09:14 -0800, Pegasus11 wrote:
> Hi Ben.
>
> Thanks for your input. Please find my comments inline.
Please don't quote your replies ! Makes it really hard to read.
>
> Benjamin Herrenschmidt wrote:
> >
> > On Tue, 2012-12-04 at 21:56 -0800, Pegasus11 wrote:
> >> Hello.
> >
Hi Ben.
Thanks for your input. Please find my comments inline.
Benjamin Herrenschmidt wrote:
>
> On Tue, 2012-12-04 at 21:56 -0800, Pegasus11 wrote:
>> Hello.
>>
>> Ive been trying to understand how an hash PTE is updated. Im on a
>> PPC970MP
>> machine which using the IBM PowerPC 604e core.
On Tue, 2012-12-04 at 21:56 -0800, Pegasus11 wrote:
> Hello.
>
> Ive been trying to understand how an hash PTE is updated. Im on a PPC970MP
> machine which using the IBM PowerPC 604e core.
Ah no, the 970 is a ... 970 core :-) It's a derivative of POWER4+ which
is quite different from the old 32-
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