On 01/24/2013 05:53:51 AM, siva kumar wrote:
Thank you Scott for the reply.
May I know did u got out of this issue and can i get some brief on
what
changes they had suggested.
I wasn't the one that had the issue. Why not send an e-mail to Eran
Liberty?
-Scott
On Thu, Jan 24, 2013 at
Thank you Scott for the reply.
May I know did u got out of this issue and can i get some brief on what
changes they had suggested.
Thanks,
Siva
On Thu, Jan 24, 2013 at 3:10 AM, Scott Wood wrote:
> On 01/23/2013 11:41:26 AM, siva kumar wrote:
>
>> Hi ,
>>
>> Is there any update on this , am ge
On 01/23/2013 11:41:26 AM, siva kumar wrote:
Hi ,
Is there any update on this , am getting in to the same state .
https://lists.ozlabs.org/pipermail/linuxppc-dev/2010-October/086680.html
Eran's initial comment of "This should probably go to the Freescale
support" seems right. You can reach
Hi ,
Is there any update on this , am getting in to the same state .
https://lists.ozlabs.org/pipermail/linuxppc-dev/2010-October/086680.html
Thanks,
Sivakumar
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Eran Liberty wrote:
Eran Liberty wrote:
This should probably go to the Freescale support, as it feels like a
hardware issue yet the end result is a very frozen Linux kernel so I
post here first...
I have a programmable FPGA PCIe device connected to a Freescale's
P2020 PCIe port. As part of t
Eran Liberty wrote:
This should probably go to the Freescale support, as it feels like a
hardware issue yet the end result is a very frozen Linux kernel so I
post here first...
I have a programmable FPGA PCIe device connected to a Freescale's
P2020 PCIe port. As part of the bring-up tests, we
tiejun.chen wrote:
AFAIK we can set one bit on PEX_ERR_DISR to detect PCI Express completion
time-out. If so one interrupt should be issued. But I'm not sure if this can fix
your issue.
Tiejun
As I understand the problem, this will not help me as the CPU itself is
on hold waiting for the ass
Eran Liberty wrote:
> This should probably go to the Freescale support, as it feels like a
> hardware issue yet the end result is a very frozen Linux kernel so I
> post here first...
>
> I have a programmable FPGA PCIe device connected to a Freescale's P2020
> PCIe port. As part of the bring-up te
On Mon, Oct 18, 2010 at 3:24 AM, Eran Liberty wrote:
> In P2020 if I do any of those the CPU is left hung over the transaction.
>
> something like:
> in_le32(addr)
>
> is turned into:
> 7c 00 04 ac sync 7c 00 4c 2c lwbrx r0,0,r9
> 0c 00 00 00 twi 0,r0,0
> 4c 00 01 2c isyn
