On 07/23/2013 11:43 AM, Scott Wood wrote:
>>
>> Yes. The max divider from sys clock to i2c clcok is 32K.
>> i2c->real_clk is the clock I2C controller pumps out, not its internal
>> operation clock.
>
> 32K is the max for all implementations?
Yes, according to application note 2919 (published).
>
On 07/23/2013 10:37:46 AM, York Sun wrote:
On 07/22/2013 05:33 PM, Scott Wood wrote:
> On Mon, May 13, 2013 at 02:27:08PM -0700, York Sun wrote:
>> Erratum A-006037 indicates I2C controller executes the write to
I2CCR only
>> after it sees SCL idle for 64K cycle of internal I2C controller
clo
On 07/22/2013 05:33 PM, Scott Wood wrote:
> On Mon, May 13, 2013 at 02:27:08PM -0700, York Sun wrote:
>> Erratum A-006037 indicates I2C controller executes the write to I2CCR only
>> after it sees SCL idle for 64K cycle of internal I2C controller clocks. If
>> during this waiting period, I2C contro
On Mon, May 13, 2013 at 02:27:08PM -0700, York Sun wrote:
> Erratum A-006037 indicates I2C controller executes the write to I2CCR only
> after it sees SCL idle for 64K cycle of internal I2C controller clocks. If
> during this waiting period, I2C controller is disabled (I2CCR[MEN] set to
> 0), then
