On Friday 21 November 2008, Michael Ellerman wrote:
> By incrementing the offset we're dropping the irq. Would it be better to
> just return, and hope that the next time we come in the MSI will have
> landed in the fifo and then we can deliver it? It might be late, really
> late I guess, but that m
On Mon, 2008-11-17 at 17:10 +0100, Arnd Bergmann wrote:
> The MSI capture logic for the axon bridge can sometimes
> lose interrupts in case of high DMA and interrupt load,
> when it signals an MSI interrupt to the MPIC interrupt
> controller while we are already handling another MSI.
>
8< 8< 8<
>
On Tuesday 18 November 2008, Giora Biran wrote:
>
> Arnd,
> >> However, reading that position does not flush the DMA, so that we can
> observe stale data in the buffer.
>
> The position register is in the DCR space from which a read does not flush
> the interrupt. But it seem that reading a regis
Arnd,
>> However, reading that position does not flush the DMA, so that we can
observe stale data in the buffer.
The position register is in the DCR space from which a read does not flush
the interrupt. But it seem that reading a register mapped to the PLB5 can
flush the interrupts if the C3PO is
