On Jun 12, 2009, at 12:38 PM, Dan Williams wrote:
Kumar Gala wrote:
On Jun 12, 2009, at 4:23 AM, Li Yang wrote:
On Thu, Jun 11, 2009 at 11:17 PM, Ira
Snyder wrote:
On Wed, Jun 10, 2009 at 09:45:26PM -0500, Kumar Gala wrote:
On Apr 27, 2009, at 3:49 PM, Dan Williams wrote:
On Mon, Apr 27
Kumar Gala wrote:
On Jun 12, 2009, at 4:23 AM, Li Yang wrote:
On Thu, Jun 11, 2009 at 11:17 PM, Ira Snyder
wrote:
On Wed, Jun 10, 2009 at 09:45:26PM -0500, Kumar Gala wrote:
On Apr 27, 2009, at 3:49 PM, Dan Williams wrote:
On Mon, Apr 27, 2009 at 1:47 PM, Timur Tabi
wrote:
Adding Kumar t
On Jun 12, 2009, at 4:23 AM, Li Yang wrote:
On Thu, Jun 11, 2009 at 11:17 PM, Ira Snyder
wrote:
On Wed, Jun 10, 2009 at 09:45:26PM -0500, Kumar Gala wrote:
On Apr 27, 2009, at 3:49 PM, Dan Williams wrote:
On Mon, Apr 27, 2009 at 1:47 PM, Timur Tabi
wrote:
Adding Kumar to the CC: list, s
On Thu, Jun 11, 2009 at 11:17 PM, Ira Snyder wrote:
> On Wed, Jun 10, 2009 at 09:45:26PM -0500, Kumar Gala wrote:
>>
>> On Apr 27, 2009, at 3:49 PM, Dan Williams wrote:
>>
>>> On Mon, Apr 27, 2009 at 1:47 PM, Timur Tabi
>>> wrote:
Adding Kumar to the CC: list, since he might pick up the patch
On Wed, Jun 10, 2009 at 09:45:26PM -0500, Kumar Gala wrote:
>
> On Apr 27, 2009, at 3:49 PM, Dan Williams wrote:
>
>> On Mon, Apr 27, 2009 at 1:47 PM, Timur Tabi
>> wrote:
>>> Adding Kumar to the CC: list, since he might pick up the patch.
>>>
>>
>> Acked-by: Dan Williams
>>
>> I agree with tak
On Apr 27, 2009, at 3:49 PM, Dan Williams wrote:
On Mon, Apr 27, 2009 at 1:47 PM, Timur Tabi
wrote:
Adding Kumar to the CC: list, since he might pick up the patch.
Acked-by: Dan Williams
I agree with taking this through Kumar's tree.
I'm going through patches for .31.. Should I still
David Hawkins wrote:
>> How about FIFO RAM case?
>
> If the FIFO has a fixed address, then according to
> the user guide, the DMA controller won't generate
> a burst transaction to it.
>
> We can try confirming this if you'd like.
Like I said earlier, this driver does not support copying data to
>> You are assuming the PCI memory space is prefetchable( no side effect)
>> for DMA.
>> Is it possible that DMA is from non-prefetchable memory space?
> This should be a safe assumption for this driver. Remember, this
> driver just does offload memcpy, from one region to another. So the
> PCI m
Hi Dave,
For the DMA PCI read/line/multi-line is outbound transaction.
So according to your experiment, the 8349 PCI controller(as master)
attemp to streaming/combining the outbound transaction(treated as
prefetchable space).
Yep, with the MPC8349EA configured as a PCI Target,
and operating as
> >> You can mark the pci inbound window on the 83xx as
> >> non-prefetchable(assuming 83xx is host). On a x86 host
> >> I doubt there is any easy way to get non-prefetchable memory.
> One more note; we don't have access to a host-mode MPC8349EA,
> our boards are all targets.
Actually we also ca
> Here's a few results from DMA tests between two
> MPC8349EA boards housed in a CPCI chassis.
>
> 1. DMA mode register (DMAMRn)
> PCI read command (PRC, bits 11:10)
>
> a) DMAMRn[PRC] = 00 = PCI Read
>
>The PCI read command is 6h on the PCI bus.
>For DMA lengths of less
How about FIFO RAM case?
If the FIFO has a fixed address, then according to
the user guide, the DMA controller won't generate
a burst transaction to it.
We can try confirming this if you'd like.
Cheers,
Dave
___
Linuxppc-dev mailing list
Linuxp
> > You are assuming the PCI memory space is prefetchable( no
> > side effect) for DMA.
> > Is it possible that DMA is from non-prefetchable memory space?
>
> This should be a safe assumption for this driver. Remember, this
> driver just does offload memcpy, from one region to another. So the
>
On Mon, Apr 27, 2009 at 1:47 PM, Timur Tabi wrote:
> Adding Kumar to the CC: list, since he might pick up the patch.
>
Acked-by: Dan Williams
I agree with taking this through Kumar's tree.
___
Linuxppc-dev mailing list
Linuxppc-dev@ozlabs.org
https://
Scott Wood wrote:
> I thought the driver only used the bit if the device tree indicated it
> was an 83xx-era DMA controller?
I just wanted to make sure it didn't do anything weird. It was the only
test I could think of that didn't involve PCI.
> That said, the bits are documented as specificall
On Mon, Apr 27, 2009 at 03:04:49PM -0500, Timur Tabi wrote:
> David Hawkins wrote:
>
> > Can you give me an example of non-PCI memory that would be
> > non-prefetchable that you'd like us to try? We can see if our
> > host CPUs have an area like that ... we just need to know
> > what device to loo
Adding Kumar to the CC: list, since he might pick up the patch.
Ira Snyder wrote:
> From 73e42fa58c93de8d4d429ba8e069b60c42037b58 Mon Sep 17 00:00:00 2001
> From: Ira W. Snyder
> Date: Thu, 23 Apr 2009 16:17:54 -0700
> Subject: [PATCH] fsldma: use PCI Read Multiple command
>
> By default, the F
Timur Tabi wrote:
David Hawkins wrote:
Ira will add your comment to the body of the code near
the PRC_RM command and submit a new patch.
I'd rather have it near the top where people can see it.
Looks like Ira had the same thought :)
Dave
___
Li
David Hawkins wrote:
> Ira will add your comment to the body of the code near
> the PRC_RM command and submit a new patch.
I'd rather have it near the top where people can see it.
--
Timur Tabi
Linux kernel developer at Freescale
___
Linuxppc-dev mail
On Mon, Apr 27, 2009 at 03:26:36PM -0500, Timur Tabi wrote:
> David Hawkins wrote:
>
> > PRC_RM - PCI read multiple
> >The default PCI read command used by the DMA controller is
> >PCI Read (PCI command 6h). When the burst length is 32-bytes
> >or longer, PCI Read Line (PCI command Eh)
Hi Timur,
PRC_RM - PCI read multiple
The default PCI read command used by the DMA controller is
PCI Read (PCI command 6h). When the burst length is 32-bytes
or longer, PCI Read Line (PCI command Eh) is used (undocumented
feature of the controller). Using PCI read multiple
(PCI com
David Hawkins wrote:
> PRC_RM - PCI read multiple
>The default PCI read command used by the DMA controller is
>PCI Read (PCI command 6h). When the burst length is 32-bytes
>or longer, PCI Read Line (PCI command Eh) is used (undocumented
>feature of the controller). Using PCI read m
Hi Timur,
Would you like some sort of summary of this info for a commit
message?
That's probably overkill. I just want a sentence or two that tells
someone looking at the code casually that the behavior of reading PCI
memory might be different than what they expect.
Could you help us with t
Can you give me an example of non-PCI memory that would be
non-prefetchable that you'd like us to try? We can see if our
host CPUs have an area like that ... we just need to know
what device to look for first :)
You can mark the pci inbound window on the 83xx as non-prefetchable
(assuming 83xx
David Hawkins wrote:
> Can you give me an example of non-PCI memory that would be
> non-prefetchable that you'd like us to try? We can see if our
> host CPUs have an area like that ... we just need to know
> what device to look for first :)
H I was going to say any SOC device in the IMMR,
On Apr 27, 2009, at 3:00 PM, David Hawkins wrote:
Can you give me an example of non-PCI memory that would be
non-prefetchable that you'd like us to try? We can see if our
host CPUs have an area like that ... we just need to know
what device to look for first :)
You can mark the pci inbound wi
You can mark the pci inbound window on the 83xx as non-prefetchable
(assuming 83xx is host). On a x86 host I doubt there is any easy way
to get non-prefetchable memory.
One more note; we don't have access to a host-mode MPC8349EA,
our boards are all targets.
Cheers,
Dave
___
Can you give me an example of non-PCI memory that would be
non-prefetchable that you'd like us to try? We can see if our
host CPUs have an area like that ... we just need to know
what device to look for first :)
You can mark the pci inbound window on the 83xx as non-prefetchable
(assuming 83x
On Apr 27, 2009, at 2:48 PM, David Hawkins wrote:
Can you give me an example of non-PCI memory that would be
non-prefetchable that you'd like us to try? We can see if our
host CPUs have an area like that ... we just need to know
what device to look for first :)
You can mark the pci inbound wi
Would you like some sort of summary of this info for a commit
message?
That's probably overkill. I just want a sentence or two that tells
someone looking at the code casually that the behavior of reading PCI
memory might be different than what they expect.
Ok, will-do.
Would you like us
David Hawkins wrote:
> Would you like some sort of summary of this info for a commit
> message?
That's probably overkill. I just want a sentence or two that tells
someone looking at the code casually that the behavior of reading PCI
memory might be different than what they expect.
> Would you l
Hi all,
You are assuming the PCI memory space is prefetchable( no side effect)
for DMA. Is it possible that DMA is from non-prefetchable memory space?
This should be a safe assumption for this driver. Remember, this
driver just does offload memcpy, from one region to another. So the
PCI memo
On Mon, Apr 27, 2009 at 4:09 AM, Liu Dave-R63238 wrote:
> You are assuming the PCI memory space is prefetchable( no side effect)
> for DMA.
> Is it possible that DMA is from non-prefetchable memory space?
This should be a safe assumption for this driver. Remember, this
driver just does offload
On Mon, Apr 27, 2009 at 5:09 PM, Liu Dave-R63238 wrote:
>> By default, the Freescale 83xx DMA controller uses the PCI Read Line
>> command when reading data over the PCI bus. Setting the
>> controller to use the PCI Read Multiple command instead allows the
>> controller to read much larger bursts
> By default, the Freescale 83xx DMA controller uses the PCI Read Line
> command when reading data over the PCI bus. Setting the
> controller to use the PCI Read Multiple command instead allows the
> controller to read much larger bursts of data, which provides a
drastic
> speed increase.
IIRC, t
On Sat, Apr 25, 2009 at 2:35 AM, Ira Snyder wrote:
> By default, the Freescale 83xx DMA controller uses the PCI Read Line
> command when reading data over the PCI bus. Setting the controller to use
> the PCI Read Multiple command instead allows the controller to read much
> larger bursts of data,
36 matches
Mail list logo
