I actually take most of this back, it looks like there is a path
available so as not to fork the driver for the pseries.
Thomas Taranowski
Certified netburner consultant
baringforge.com
On Wed, Dec 15, 2010 at 12:40 PM, Thomas Taranowski
wrote:
>>
>>> There is some divergance in respect to th
>
>> There is some divergance in respect to the memory map that is non-trivial
>> that
>> I'm not sure how to handle, since it totally hoses the common fsl_rio.c
>> structures.
>> I think I want to create a new set that's p2020 specific, but has potential
>> to be
>> shared with the other QorIQ
Thomas Taranowski wrote:
> I'm planning to add support for the multiple(2) mports supported by
> the Freescale p2020 processor. I'm currently looking at the fsl layer
> to add in support for multiple port enumeration, and work up from
> there. It looks like the upper layers already have at leas
> Subject: RapidIO: multiple mport support for QorIQ
>
> I'm planning to add support for the multiple(2) mports supported by the
> Freescale
> p2020 processor. I'm currently looking at the fsl layer to add in support for
> multiple port enumeration, and work up fr
I'm planning to add support for the multiple(2) mports supported by
the Freescale p2020 processor. I'm currently looking at the fsl layer
to add in support for multiple port enumeration, and work up from
there. It looks like the upper layers already have at least partial
support for this. My que
