Hi, Ben,
2009/12/7, Benjamin Herrenschmidt :
>
> Cache coherency bugs in the chipset or HW bugs in DBDMA, we've been
> seeing those on/off on those old apple chipsets...
>
> Try forcing a 32 bytes alignment ?
>
You're thinking of placing the DMA descriptors on different cache lines?
That's excact
On Mon, 2009-12-07 at 00:36 +0200, Risto Suominen wrote:
> I post this in hope that somebody could shed some light on how should
> the DMA work in conjunction with the MACE ethernet controller. I find
> difficult to understand why it does not work in my case:
>
> What happens? First two bytes of a
Hi, everybody,
I post this in hope that somebody could shed some light on how should
the DMA work in conjunction with the MACE ethernet controller. I find
difficult to understand why it does not work in my case:
What happens? First two bytes of a received frame are not what they
should be in more
