On Friday 29 April 2022 22:57:03 Michael Ellerman wrote:
> Pali Rohár writes:
> > Hello!
> >
> > I started playing with PowerPC e500 architecture, it is something really
> > new for me and I suspect that I found a bug in U-Boot code which
> > configures L2 cache as initial SRAM (L2 with locked lin
Pali Rohár writes:
> Hello!
>
> I started playing with PowerPC e500 architecture, it is something really
> new for me and I suspect that I found a bug in U-Boot code which
> configures L2 cache as initial SRAM (L2 with locked lines).
>
> U-Boot code for the first half of L2 cache sets Caching-inhi
Hello!
I started playing with PowerPC e500 architecture, it is something really
new for me and I suspect that I found a bug in U-Boot code which
configures L2 cache as initial SRAM (L2 with locked lines).
U-Boot code for the first half of L2 cache sets Caching-inhibited
(MAS2_I) in TLB and for se
