Paul Mackerras <[EMAIL PROTECTED]> wrote on 05/15/2008 06:02:03 PM:
> Corey J Ashford writes:
>
> > Thanks for the feedback. I don't believe I need a separate flag,
because
> > the PMU interrupt (via the PMAO bit) will still be pending when
interrupts
> > are hard enabled again, and the handler
Paul Mackerras <[EMAIL PROTECTED]> wrote on 05/15/2008 06:02:03 PM:
> Corey J Ashford writes:
>
> > Thanks for the feedback. I don't believe I need a separate flag,
because
> > the PMU interrupt (via the PMAO bit) will still be pending when
interrupts
> > are hard enabled again, and the handle
Corey J Ashford writes:
> Thanks for the feedback. I don't believe I need a separate flag, because
> the PMU interrupt (via the PMAO bit) will still be pending when interrupts
> are hard enabled again, and the handler will be reentered automatically.
If that were the case then we wouldn't have h
Paul Mackerras <[EMAIL PROTECTED]> wrote on 05/15/2008 04:36:02 PM:
> Corey J Ashford writes:
>
> > Ideally, what I'm looking for is something that mimics the operation of
> > MASKABLE_EXCEPTION_PSERIES.
> > I've been looking at the kernel code (entry_64.S, exception.h,
head_64.S)
> > but am fin
Corey J Ashford writes:
> Ideally, what I'm looking for is something that mimics the operation of
> MASKABLE_EXCEPTION_PSERIES.
> I've been looking at the kernel code (entry_64.S, exception.h, head_64.S)
> but am finding it quite complicated and hard to follow, particularly in the
> area of interr
Just FYI: I just tried out the code I suggested below, and it does not
work; it results in a system hang. I have spent some time analyzing why
this doesn't work as I expected, but so far I haven't been able to figure
it out.
Regards,
Corey Ashford
Software Engineer
IBM Linux Technology Center,
Hi Benjamin and Olaf,
Thanks for the suggestions.
Ideally, what I'm looking for is something that mimics the operation of
MASKABLE_EXCEPTION_PSERIES.
I've been looking at the kernel code (entry_64.S, exception.h, head_64.S)
but am finding it quite complicated and hard to follow, particularly in t
On Tue, 2008-05-13 at 15:26 -0700, Corey Ashford wrote:
> The perfmon2 code is available here:
> http://sourceforge.net/project/showfiles.php?group_id=144822
>
> perfmon2's interrupt handler does have a single entry point. Could I
> somehow mimic what the MASKABLE_EXCEPTION_PSERIES macro does
Corey J Ashford wrote:
On May 13, 2008, at 5:05 PM, Corey Ashford wrote:
Hello,
One of the things I've been working on is porting perfmon2 to ppc64.
We've made a fair amount of progress on it, and support is available
in libpfm and the perfmon2 kernel patch.
One of the things we had to work a
On May 13, 2008, at 5:05 PM, Corey Ashford wrote:
Hello,
One of the things I've been working on is porting perfmon2 to ppc64.
We've made a fair amount of progress on it, and support is available
in libpfm and the perfmon2 kernel patch.
One of the things we had to work around was the "lazy
Hello,
One of the things I've been working on is porting perfmon2 to ppc64.
We've made a fair amount of progress on it, and support is available in
libpfm and the perfmon2 kernel patch.
One of the things we had to work around was the "lazy interrupt
disabling" mechanism in ppc64 Linux. The
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