Re: Detecting LD/ST instruction

2013-08-25 Thread Michael Neuling
Sukadev Bhattiprolu wrote: > Michael Neuling [mi...@neuling.org] wrote: > | > I am working on implementing the 'perf mem' command for Power > | > systems. This would for instance, let us know where in the memory > | > hierarchy (L1, L2, Local RAM etc) the data for a load/store > | > instruction w

Re: Detecting LD/ST instruction

2013-08-24 Thread Sukadev Bhattiprolu
Michael Neuling [mi...@neuling.org] wrote: | > I am working on implementing the 'perf mem' command for Power | > systems. This would for instance, let us know where in the memory | > hierarchy (L1, L2, Local RAM etc) the data for a load/store | > instruction was found (hit). | > | > On Power7, if

Re: Detecting LD/ST instruction

2013-08-22 Thread Michael Neuling
> I am working on implementing the 'perf mem' command for Power > systems. This would for instance, let us know where in the memory > hierarchy (L1, L2, Local RAM etc) the data for a load/store > instruction was found (hit). > > On Power7, if the mcmcra[DCACHE_MISS] is clear _and_ the > instructio

Detecting LD/ST instruction

2013-08-22 Thread Sukadev Bhattiprolu
I am working on implementing the 'perf mem' command for Power systems. This would for instance, let us know where in the memory hierarchy (L1, L2, Local RAM etc) the data for a load/store instruction was found (hit). On Power7, if the mcmcra[DCACHE_MISS] is clear _and_ the instruction is a load/s