On Tue, 2012-09-18 at 16:50 -0500, Ayman El-Khashab wrote:
> I've got a design that is 405EXr based so its got 32 bit
> address space. We have an FPGA that sits on our pcie bus
> and we want it to have 2 BARs with 1G of space and maybe
> 256MB of space. I cannot figure out what I need to change
>
I've got a design that is 405EXr based so its got 32 bit
address space. We have an FPGA that sits on our pcie bus
and we want it to have 2 BARs with 1G of space and maybe
256MB of space. I cannot figure out what I need to change
in the kernel/dts to make this work.
Right now, if I go over 512M
