rg; Mike Turquette
> Subject: Re: [v3] powerpc/mpc85xx: Update the clock device tree nodes
>
> On Mon, 2013-08-26 at 21:49 -0500, Tang Yuantian-B29983 wrote:
> > > > > > + };
> > > > > > + pll1: pll1@820 {
> > > > >
On Mon, 2013-08-26 at 21:49 -0500, Tang Yuantian-B29983 wrote:
> > > > > + };
> > > > > + pll1: pll1@820 {
> > > > > + #clock-cells = <1>;
> > > > > + reg = <0x820>;
> > > > > + compatible = "fsl,core-pll-clock";
>
> > > > + };
> > > > + pll1: pll1@820 {
> > > > + #clock-cells = <1>;
> > > > + reg = <0x820>;
> > > > + compatible = "fsl,core-pll-clock";
> > > > + clocks = <&clockgen>;
> > > > +
On Sun, 2013-08-25 at 21:42 -0500, Tang Yuantian-B29983 wrote:
> > >
> > > clockgen: global-utilities@e1000 {
> > > - compatible = "fsl,b4420-clockgen", "fsl,qoriq-clockgen-2.0";
> > > + compatible = "fsl,b4420-clockgen", "fsl,qoriq-clockgen-2.0",
> > > +
> >
> > clockgen: global-utilities@e1000 {
> > - compatible = "fsl,b4420-clockgen", "fsl,qoriq-clockgen-2.0";
> > + compatible = "fsl,b4420-clockgen", "fsl,qoriq-clockgen-2.0",
> > + "fixed-clock";
> > + clock-output-names = "sysclk";
>
On Thu, Jun 06, 2013 at 09:06:51AM +0800, tang yuantian wrote:
> From: Tang Yuantian
>
> The following SoCs will be affected: p2041, p3041, p4080,
> p5020, p5040, b4420, b4860, t4240
>
> Signed-off-by: Tang Yuantian
> Signed-off-by: Li Yang
>
> ---
> v3:
> - fix typo
> v2:
> - add
From: Tang Yuantian
The following SoCs will be affected: p2041, p3041, p4080,
p5020, p5040, b4420, b4860, t4240
Signed-off-by: Tang Yuantian
Signed-off-by: Li Yang
---
v3:
- fix typo
v2:
- add t4240, b4420, b4860 support
- remove pll/4 clock from p2041, p3041 and p5020
