On Wed, 13 Sep 2017 02:05:53 +1000
Nicholas Piggin wrote:
> There are two complications. The first is that sreset from stop states
> come in with SRR1 set to do a powersave wakeup, with an sreset reason
> encoded.
>
> The second is that threads on the same core can't be signalled directly
> so w
On Thu, 14 Sep 2017 04:32:28 PM Nicholas Piggin wrote:
> On Thu, 14 Sep 2017 12:24:49 +1000
> Benjamin Herrenschmidt wrote:
>
> > On Wed, 2017-09-13 at 23:13 +1000, Nicholas Piggin wrote:
> > > On Wed, 13 Sep 2017 02:05:53 +1000
> > > Nicholas Piggin wrote:
> > >
> > > > There are two complic
On Thu, 14 Sep 2017 12:24:49 +1000
Benjamin Herrenschmidt wrote:
> On Wed, 2017-09-13 at 23:13 +1000, Nicholas Piggin wrote:
> > On Wed, 13 Sep 2017 02:05:53 +1000
> > Nicholas Piggin wrote:
> >
> > > There are two complications. The first is that sreset from stop states
> > > come in with SR
On Wed, 2017-09-13 at 23:13 +1000, Nicholas Piggin wrote:
> On Wed, 13 Sep 2017 02:05:53 +1000
> Nicholas Piggin wrote:
>
> > There are two complications. The first is that sreset from stop states
> > come in with SRR1 set to do a powersave wakeup, with an sreset reason
> > encoded.
> >
> > The
On Wed, 13 Sep 2017 02:05:53 +1000
Nicholas Piggin wrote:
> There are two complications. The first is that sreset from stop states
> come in with SRR1 set to do a powersave wakeup, with an sreset reason
> encoded.
>
> The second is that threads on the same core can't be signalled directly
> so w
There are two complications. The first is that sreset from stop states
come in with SRR1 set to do a powersave wakeup, with an sreset reason
encoded.
The second is that threads on the same core can't be signalled directly
so we must designate a bounce CPU to reflect the IPI back.
---
arch/powerpc
