On Jun 6, 2009, at 5:42 PM, Benjamin Herrenschmidt wrote:
On Sun, 2009-06-07 at 00:07 +0200, Wolfgang Denk wrote:
Dear David Jander,
In message <200903161652.09747.david.jan...@protonic.nl> you wrote:
Complete workaround for DTLB errata in e300c2/c3/c4 processors.
Due to the bug, the hardwa
On Sun, 2009-06-07 at 00:07 +0200, Wolfgang Denk wrote:
> Dear David Jander,
>
> In message <200903161652.09747.david.jan...@protonic.nl> you wrote:
> > Complete workaround for DTLB errata in e300c2/c3/c4 processors.
> >
> > Due to the bug, the hardware-implemented LRU algorythm always goes to wa
Dear David Jander,
In message <200903161652.09747.david.jan...@protonic.nl> you wrote:
> Complete workaround for DTLB errata in e300c2/c3/c4 processors.
>
> Due to the bug, the hardware-implemented LRU algorythm always goes to way
> 1 of the TLB. This fix implements the proposed software workarou
On Mar 17, 2009, at 5:38 AM, David Jander wrote:
On Monday 16 March 2009 19:05:00 Kumar Gala wrote:
On Mar 16, 2009, at 10:52 AM, David Jander wrote:
Complete workaround for DTLB errata in e300c2/c3/c4 processors.
Due to the bug, the hardware-implemented LRU algorythm always goes
to way
1 of
On Monday 16 March 2009 19:05:00 Kumar Gala wrote:
> On Mar 16, 2009, at 10:52 AM, David Jander wrote:
> > Complete workaround for DTLB errata in e300c2/c3/c4 processors.
> >
> > Due to the bug, the hardware-implemented LRU algorythm always goes
> > to way
> > 1 of the TLB. This fix implements the
On Mar 16, 2009, at 10:52 AM, David Jander wrote:
Complete workaround for DTLB errata in e300c2/c3/c4 processors.
Due to the bug, the hardware-implemented LRU algorythm always goes
to way
1 of the TLB. This fix implements the proposed software workaround in
form of a LRW table for chosing t
On Mar 16, 2009, at 11:09 AM, David Jander wrote:
In this patch, I placed the LRW table in SPRG6 like before, but
Kumar's code
seems a little more compact, so I decided to use that one and fix
it ;-)
It's a pity we seem to have one register short in the handler, so we
need to
load SPR
On Mon, 2009-03-16 at 16:52 +0100, David Jander wrote:
> Complete workaround for DTLB errata in e300c2/c3/c4 processors.
>
> Due to the bug, the hardware-implemented LRU algorythm always goes to way
> 1 of the TLB. This fix implements the proposed software workaround in
> form of a LRW table for c
In this patch, I placed the LRW table in SPRG6 like before, but Kumar's code
seems a little more compact, so I decided to use that one and fix it ;-)
It's a pity we seem to have one register short in the handler, so we need to
load SPRN_SRR1 twice :-(
Allthough the code-path now has 1 instruct
Complete workaround for DTLB errata in e300c2/c3/c4 processors.
Due to the bug, the hardware-implemented LRU algorythm always goes to way
1 of the TLB. This fix implements the proposed software workaround in
form of a LRW table for chosing the TLB-way.
Signed-off-by: Kumar Gala
Signed-off-by: Da
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