> I'm ok for it to be taken care of in u-boot for now. However, if we
> later plan to add power management support to this block. We probably
> have to do it in kernel.
In that case, can't it be just saving/restoring ? That's easier than
supporting full configuration of random user setups
Ben.
On Nov 20, 2007, at 10:01 PM, Kumar Gala wrote:
>>> Upon further review of all this I don't think this belongs in
>>> the kernel at all. This is one time setup and should be done
>>> in firmware.
>>
>> I'm ok for it to be taken care of in u-boot for now. However, if we
>> later plan to add powe
>> Upon further review of all this I don't think this belongs in
>> the kernel at all. This is one time setup and should be done
>> in firmware.
>
> I'm ok for it to be taken care of in u-boot for now. However, if we
> later plan to add power management support to this block. We probably
> have
> On Oct 19, 2007, at 10:35 AM, Grant Likely wrote:
>
> > On 10/19/07, Li Yang <[EMAIL PROTECTED]> wrote:
> >> The SerDes(serializer/deserializer) PHY block is a new SoC
> block used
> >> in Freescale chips to support multiple serial interfaces,
> such as PCI
> >> Express, SGMII, SATA.
> >
> > T
> -Original Message-
> From: Kumar Gala [mailto:[EMAIL PROTECTED]
> Sent: Wednesday, November 21, 2007 11:32 AM
> To: Li Yang
> Cc: Paul Mackerras; linuxppc-dev@ozlabs.org; Grant Likely
> Subject: Re: [PATCH v7 3/9] add Freescale SerDes PHY support
>
>
> O
On Oct 19, 2007, at 10:35 AM, Grant Likely wrote:
> On 10/19/07, Li Yang <[EMAIL PROTECTED]> wrote:
>> The SerDes(serializer/deserializer) PHY block is a new SoC block used
>> in Freescale chips to support multiple serial interfaces, such as PCI
>> Express, SGMII, SATA.
>
> This looks like board
On 10/19/07, Li Yang <[EMAIL PROTECTED]> wrote:
> The SerDes(serializer/deserializer) PHY block is a new SoC block used
> in Freescale chips to support multiple serial interfaces, such as PCI
> Express, SGMII, SATA.
This looks like board setup behaviour. Shouldn't setting this up be
the responsib
The SerDes(serializer/deserializer) PHY block is a new SoC block used
in Freescale chips to support multiple serial interfaces, such as PCI
Express, SGMII, SATA.
Signed-off-by: Li Yang <[EMAIL PROTECTED]>
---
arch/powerpc/platforms/Kconfig |7 ++
arch/powerpc/sysdev/Makefile |1 +
a
