On Sun, Mar 28, 2021 at 7:14 PM Christophe Leroy
wrote:
>
>
>
> Le 28/03/2021 à 08:30, guo...@kernel.org a écrit :
> > From: Guo Ren
> >
> > We don't have native hw xchg16 instruction, so let qspinlock
> > generic code to deal with it.
>
> We have lharx/sthcx pair on some versions of powerpc.
>
>
Le 28/03/2021 à 08:30, guo...@kernel.org a écrit :
From: Guo Ren
We don't have native hw xchg16 instruction, so let qspinlock
generic code to deal with it.
We have lharx/sthcx pair on some versions of powerpc.
See
https://patchwork.ozlabs.org/project/linuxppc-dev/patch/20201107032328.245
From: Guo Ren
We don't have native hw xchg16 instruction, so let qspinlock
generic code to deal with it.
Using the full-word atomic xchg instructions implement xchg16 has
the semantic risk for atomic operations.
This patch cancels the dependency of on qspinlock generic code on
architecture's xc
