Re: [PATCH v5 3/4] arm64: topology: Support SMT control on ACPI based system

2024-09-12 Thread Michal Suchánek
Hello, On Thu, Sep 12, 2024 at 01:59:16PM +0200, Morten Rasmussen wrote: > On Fri, Sep 06, 2024 at 04:36:30PM +0800, Yicong Yang wrote: > > On 2024/9/6 15:06, Morten Rasmussen wrote: > > > Hi Yicong, > > > > > > On Thu, Sep 05, 2024 at 08:02:20PM +0800, Yicong Yang wrote: > > >> On 2024/9/5 16:34

Re: [PATCH v5 3/4] arm64: topology: Support SMT control on ACPI based system

2024-09-12 Thread Morten Rasmussen
On Fri, Sep 06, 2024 at 04:36:30PM +0800, Yicong Yang wrote: > On 2024/9/6 15:06, Morten Rasmussen wrote: > > Hi Yicong, > > > > On Thu, Sep 05, 2024 at 08:02:20PM +0800, Yicong Yang wrote: > >> On 2024/9/5 16:34, Pierre Gondois wrote: > >>> Hello Yicong, > >>> > >>> If a platform has CPUs with: >

Re: [PATCH v5 3/4] arm64: topology: Support SMT control on ACPI based system

2024-09-06 Thread Morten Rasmussen
Hi Yicong, On Thu, Sep 05, 2024 at 08:02:20PM +0800, Yicong Yang wrote: > On 2024/9/5 16:34, Pierre Gondois wrote: > > Hello Yicong, > > > > If a platform has CPUs with: > > - 1 thread > > - X (!= 1) threads > > Then I think that the asymmetry is not detected > > Ah ok, I only handle the case wh

Re: [PATCH v5 3/4] arm64: topology: Support SMT control on ACPI based system

2024-09-06 Thread Yicong Yang
On 2024/9/6 15:06, Morten Rasmussen wrote: > Hi Yicong, > > On Thu, Sep 05, 2024 at 08:02:20PM +0800, Yicong Yang wrote: >> On 2024/9/5 16:34, Pierre Gondois wrote: >>> Hello Yicong, >>> >>> If a platform has CPUs with: >>> - 1 thread >>> - X (!= 1) threads >>> Then I think that the asymmetry is n

Re: [PATCH v5 3/4] arm64: topology: Support SMT control on ACPI based system

2024-09-05 Thread Yicong Yang
On 2024/9/5 16:34, Pierre Gondois wrote: > Hello Yicong, > Wondering if we can avoid this 2nd loop. Greg express the worries of looping twice on large scale system in v1. Maybe we could use the hetero_id and get the necessary information in one loop, I need further think

Re: [PATCH v5 3/4] arm64: topology: Support SMT control on ACPI based system

2024-09-05 Thread Pierre Gondois
Hello Yicong, Wondering if we can avoid this 2nd loop. Greg express the worries of looping twice on large scale system in v1. Maybe we could use the hetero_id and get the necessary information in one loop, I need further think. I found this comments (not sure this is what you are refering to

Re: [PATCH v5 3/4] arm64: topology: Support SMT control on ACPI based system

2024-09-03 Thread Yicong Yang
On 2024/9/2 15:43, Pierre Gondois wrote: > Hello Yicong > > On 8/30/24 11:35, Yicong Yang wrote: >> On 2024/8/29 20:46, Pierre Gondois wrote: >>> Hello Yicong, >>> >>> On 8/29/24 09:40, Yicong Yang wrote: Hi Pierre, On 2024/8/27 23:40, Pierre Gondois wrote: > Hello Yicong, >

Re: [PATCH v5 3/4] arm64: topology: Support SMT control on ACPI based system

2024-09-02 Thread Pierre Gondois
Hello Yicong On 8/30/24 11:35, Yicong Yang wrote: On 2024/8/29 20:46, Pierre Gondois wrote: Hello Yicong, On 8/29/24 09:40, Yicong Yang wrote: Hi Pierre, On 2024/8/27 23:40, Pierre Gondois wrote: Hello Yicong, IIUC we are looking for the maximum number of threads a CPU can have in the platf

Re: [PATCH v5 3/4] arm64: topology: Support SMT control on ACPI based system

2024-08-30 Thread Yicong Yang
On 2024/8/29 20:46, Pierre Gondois wrote: > Hello Yicong, > > On 8/29/24 09:40, Yicong Yang wrote: >> Hi Pierre, >> >> On 2024/8/27 23:40, Pierre Gondois wrote: >>> Hello Yicong, >>> IIUC we are looking for the maximum number of threads a CPU can have >>> in the platform. But is is actually possib

Re: [PATCH v5 3/4] arm64: topology: Support SMT control on ACPI based system

2024-08-29 Thread Pierre Gondois
Hello Yicong, On 8/29/24 09:40, Yicong Yang wrote: Hi Pierre, On 2024/8/27 23:40, Pierre Gondois wrote: Hello Yicong, IIUC we are looking for the maximum number of threads a CPU can have in the platform. But is is actually possible to have a platform with CPUs not having the same number of thr

Re: [PATCH v5 3/4] arm64: topology: Support SMT control on ACPI based system

2024-08-29 Thread Yicong Yang
Hi Pierre, On 2024/8/27 23:40, Pierre Gondois wrote: > Hello Yicong, > IIUC we are looking for the maximum number of threads a CPU can have > in the platform. But is is actually possible to have a platform with > CPUs not having the same number of threads ? > I was thinking of the heterogenous p

Re: [PATCH v5 3/4] arm64: topology: Support SMT control on ACPI based system

2024-08-27 Thread Pierre Gondois
Hello Yicong, IIUC we are looking for the maximum number of threads a CPU can have in the platform. But is is actually possible to have a platform with CPUs not having the same number of threads ? For instance kernel/cpu.c::cpu_smt_num_threads_valid() will check that the number of threads is eith

Re: [PATCH v5 3/4] arm64: topology: Support SMT control on ACPI based system

2024-08-22 Thread Dietmar Eggemann
On 19/08/2024 09:03, Yicong Yang wrote: > On 2024/8/16 23:55, Dietmar Eggemann wrote: >> On 06/08/2024 10:53, Yicong Yang wrote: >>> From: Yicong Yang [...] >> So the xarray contains one element for each core_id with the information >> how often the core_id occurs? I assume you have to iterate o

Re: [PATCH v5 3/4] arm64: topology: Support SMT control on ACPI based system

2024-08-19 Thread Yicong Yang
On 2024/8/16 23:55, Dietmar Eggemann wrote: > On 06/08/2024 10:53, Yicong Yang wrote: >> From: Yicong Yang >> >> For ACPI we'll build the topology from PPTT and we cannot directly >> get the SMT number of each core. Instead using a temporary xarray >> to record the SMT number of each core when bui

Re: [PATCH v5 3/4] arm64: topology: Support SMT control on ACPI based system

2024-08-16 Thread Dietmar Eggemann
On 06/08/2024 10:53, Yicong Yang wrote: > From: Yicong Yang > > For ACPI we'll build the topology from PPTT and we cannot directly > get the SMT number of each core. Instead using a temporary xarray > to record the SMT number of each core when building the topology > and we can know the largest S

[PATCH v5 3/4] arm64: topology: Support SMT control on ACPI based system

2024-08-06 Thread Yicong Yang
From: Yicong Yang For ACPI we'll build the topology from PPTT and we cannot directly get the SMT number of each core. Instead using a temporary xarray to record the SMT number of each core when building the topology and we can know the largest SMT number in the system. Then we can enable the supp