H v5] powerpc/mpc85xx: Update the clock nodes in device
> tree
>
> On Sun, 2013-10-20 at 21:55 -0500, Tang Yuantian-B29983 wrote:
> > I didn't see how your suggestion is a better matching.
> >
> > OSC > PLL1 > mux > CPU
> > |
On Sun, 2013-10-20 at 21:55 -0500, Tang Yuantian-B29983 wrote:
> I didn't see how your suggestion is a better matching.
>
> OSC > PLL1 > mux > CPU
> | |
> |--> PLL2 --|
>
> As your suggestion, the clock tree looks like the above.
> In this case,
> > +1. Clock Block Binding
> > +
> > +Required properties:
> > +- compatible: Should include one or more of the following:
> > + - "fsl,-clockgen": for chip specific clock block
> > + - "fsl,qoriq-clockgen-[1,2].x": for chassis 1.x and 2.x clock
> > +- reg: Offset and length of the clock regis
On Wed, 9 Oct 2013 14:38:24 +0800, wrote:
> From: Tang Yuantian
>
> The following SoCs will be affected: p2041, p3041, p4080,
> p5020, p5040, b4420, b4860, t4240
>
> Signed-off-by: Tang Yuantian
> Signed-off-by: Li Yang
> ---
> v5:
> - refine the binding document
> - update the co
; Subject: Re: [PATCH v5] powerpc/mpc85xx: Update the clock nodes in device
> tree
>
> On Sat, Oct 12, 2013 at 04:40:06AM +0100, Tang Yuantian-B29983 wrote:
> > Thanks for your review.
> >
> > >
> > > >
> > > > > > +- reg: Offset and lengt
On Sat, Oct 12, 2013 at 04:40:06AM +0100, Tang Yuantian-B29983 wrote:
> Thanks for your review.
>
> >
> > >
> > > > > +- reg: Offset and length of the clock register set
> > > > > +- clock-frequency: Indicates input clock frequency of clock block.
> > > > > + Will be set by u-boot
> > > >
>
> > > > >
> > > > > It's still selecting from multiple PLLs.
> > > > >
> > > > > > I don't know whether "divider" module exists or not. If it
> > > > > > exists, it should be part of PLL or between PLL and MUX.
> > > > > > wherever it was, the
> > > > > device tree binding is appropriate.
> > > > >
On Thu, 2013-10-17 at 21:06 -0500, Tang Yuantian-B29983 wrote:
> > On Wed, 2013-10-16 at 21:08 -0500, Tang Yuantian-B29983 wrote:
> > > > > > That shows the dividers as being somewhere in between the PLL
> > > > > > and the
> > > > MUX.
> > > > > > The MUX is where the divider is selected. There's
> On Wed, 2013-10-16 at 21:08 -0500, Tang Yuantian-B29983 wrote:
> > > > > That shows the dividers as being somewhere in between the PLL
> > > > > and the
> > > MUX.
> > > > > The MUX is where the divider is selected. There's nothing in
> > > > > the PLL's programming interface that relates to the
On Wed, 2013-10-16 at 21:08 -0500, Tang Yuantian-B29983 wrote:
> > > > That shows the dividers as being somewhere in between the PLL and the
> > MUX.
> > > > The MUX is where the divider is selected. There's nothing in the
> > > > PLL's programming interface that relates to the dividers. As such
> > > That shows the dividers as being somewhere in between the PLL and the
> MUX.
> > > The MUX is where the divider is selected. There's nothing in the
> > > PLL's programming interface that relates to the dividers. As such
> > > it's simpler to model it as being part of the MUX.
> > >
> > > -S
On Tue, 2013-10-15 at 21:57 -0500, Tang Yuantian-B29983 wrote:
> > > > > >
> > > > > The device tree makes that quite clear.
> > > >
> > > > You chose to model it that way in the device tree; that doesn't make
> > > > it clear that the hardware works that way or that it's a good way to
> > > > mode
> > > > >
> > > > The device tree makes that quite clear.
> > >
> > > You chose to model it that way in the device tree; that doesn't make
> > > it clear that the hardware works that way or that it's a good way to
> > > model it.
> > >
> > > > Each PLL has several output which MUX node can take fro
pc-dev@lists.ozlabs.org; Li Yang-Leo-R58472
> > Subject: Re: [PATCH v5] powerpc/mpc85xx: Update the clock nodes in device
> > tree
> >
> > On Fri, 2013-10-11 at 21:52 -0500, Tang Yuantian-B29983 wrote:
> > > Thanks for your review.
> > >
> > > >
t; To: Mark Rutland
> > > Cc: Tang Yuantian-B29983; devicet...@vger.kernel.org; linuxppc-
> > > d...@lists.ozlabs.org; Li Yang-Leo-R58472
> > > Subject: Re: [PATCH v5] powerpc/mpc85xx: Update the clock nodes in
> > > device tree
> > >
> > > I'm n
linuxppc-
> > d...@lists.ozlabs.org; Li Yang-Leo-R58472
> > Subject: Re: [PATCH v5] powerpc/mpc85xx: Update the clock nodes in device
> > tree
> >
> > I'm not sure I understand the "_0"/"_1" part, though. Doesn't each PLL
> > just
Thanks for your review.
>
> >
> > > > +- reg: Offset and length of the clock register set
> > > > +- clock-frequency: Indicates input clock frequency of clock block.
> > > > + Will be set by u-boot
> > >
> > > Why does the fact this is set by u-boot matter to the binding?
> > >
> > OK, I wi
Thanks for your review.
> -Original Message-
> From: Wood Scott-B07421
> Sent: 2013年10月12日 星期六 3:08
> To: Tang Yuantian-B29983
> Cc: ga...@kernel.crashing.org; devicet...@vger.kernel.org; linuxppc-
> d...@lists.ozlabs.org
> Subject: Re: [PATCH v5] powerpc/mpc85xx: U
gt; -Original Message-
> > > > From: Mark Rutland [mailto:mark.rutl...@arm.com]
> > > > Sent: 2013年10月10日 星期四 18:04
> > > > To: Tang Yuantian-B29983
> > > > Cc: ga...@kernel.crashing.org; linuxppc-dev@lists.ozlabs.org;
> > > > device
On Wed, 2013-10-09 at 14:38 +0800, yuantian.t...@freescale.com wrote:
> From: Tang Yuantian +/ {
> + clockgen: global-utilities@e1000 {
> + compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
> + reg = <0xe1000 0x1000>;
> + clock-frequency = <0>;
>
..@arm.com]
> > > Sent: 2013年10月10日 星期四 18:04
> > > To: Tang Yuantian-B29983
> > > Cc: ga...@kernel.crashing.org; linuxppc-dev@lists.ozlabs.org;
> > > devicet...@vger.kernel.org; Li Yang-Leo-R58472
> > > Subject: Re: [PATCH v5] powerpc/mpc85xx: Update
> > Cc: ga...@kernel.crashing.org; linuxppc-dev@lists.ozlabs.org;
> > devicet...@vger.kernel.org; Li Yang-Leo-R58472
> > Subject: Re: [PATCH v5] powerpc/mpc85xx: Update the clock nodes in device
> > tree
> >
> > On Wed, Oct 09, 2013 at 07:38:24AM +0
Li Yang-Leo-R58472
> Subject: Re: [PATCH v5] powerpc/mpc85xx: Update the clock nodes in device
> tree
>
> On Wed, Oct 09, 2013 at 07:38:24AM +0100, yuantian.t...@freescale.com
> wrote:
> > From: Tang Yuantian
> >
> > The following SoCs will be affected: p2041,
On Wed, Oct 09, 2013 at 07:38:24AM +0100, yuantian.t...@freescale.com wrote:
> From: Tang Yuantian
>
> The following SoCs will be affected: p2041, p3041, p4080,
> p5020, p5040, b4420, b4860, t4240
>
> Signed-off-by: Tang Yuantian
> Signed-off-by: Li Yang
> ---
> v5:
> - refine the bindin
From: Tang Yuantian
The following SoCs will be affected: p2041, p3041, p4080,
p5020, p5040, b4420, b4860, t4240
Signed-off-by: Tang Yuantian
Signed-off-by: Li Yang
---
v5:
- refine the binding document
- update the compatible string
v4:
- add binding document
-
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